1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/interrupt-c 4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Texas Instruments K3 Interrupt Aggregat 7 title: Texas Instruments K3 Interrupt Aggregator
8 8
9 maintainers: 9 maintainers:
10 - Lokesh Vutla <lokeshvutla@ti.com> 10 - Lokesh Vutla <lokeshvutla@ti.com>
11 11
12 allOf: 12 allOf:
13 - $ref: /schemas/arm/keystone/ti,k3-sci-comm 13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
14 14
15 description: | 15 description: |
16 The Interrupt Aggregator (INTA) provides a c 16 The Interrupt Aggregator (INTA) provides a centralized machine
17 which handles the termination of system even 17 which handles the termination of system events to that they can
18 be coherently processed by the host(s) in th 18 be coherently processed by the host(s) in the system. A maximum
19 of 64 events can be mapped to a single inter 19 of 64 events can be mapped to a single interrupt.
20 20
21 Interrupt Aggr 21 Interrupt Aggregator
22 +---------------------- 22 +-----------------------------------------+
23 | Intmap 23 | Intmap VINT |
24 | +--------------+ +-- 24 | +--------------+ +------------+ |
25 m ------>| | vint | bit | | 0 25 m ------>| | vint | bit | | 0 |.....|63| vint0 |
26 . | +--------------+ +-- 26 . | +--------------+ +------------+ | +------+
27 . | . 27 . | . . | | HOST |
28 Globalevents ------>| . 28 Globalevents ------>| . . |----->| IRQ |
29 . | . 29 . | . . | | CTRL |
30 . | . 30 . | . . | +------+
31 n ------>| +--------------+ +-- 31 n ------>| +--------------+ +------------+ |
32 | | vint | bit | | 0 32 | | vint | bit | | 0 |.....|63| vintx |
33 | +--------------+ +-- 33 | +--------------+ +------------+ |
34 | 34 | |
35 | Unmap 35 | Unmap |
36 | +--------------+ 36 | +--------------+ |
37 Unmapped events ---->| | umapidx |----- 37 Unmapped events ---->| | umapidx |-------------------------> Globalevents
38 | +--------------+ 38 | +--------------+ |
39 | 39 | |
40 +---------------------- 40 +-----------------------------------------+
41 41
42 Configuration of these Intmap registers that 42 Configuration of these Intmap registers that maps global events to vint is
43 done by a system controller (like the Device 43 done by a system controller (like the Device Memory and Security Controller
44 on AM654 SoC). Driver should request the sys 44 on AM654 SoC). Driver should request the system controller to get the range
45 of global events and vints assigned to the r 45 of global events and vints assigned to the requesting host. Management
46 of these requested resources should be handl 46 of these requested resources should be handled by driver and requests
47 system controller to map specific global eve 47 system controller to map specific global event to vint, bit pair.
48 48
49 Communication between the host processor run 49 Communication between the host processor running an OS and the system
50 controller happens through a protocol called 50 controller happens through a protocol called TI System Control Interface
51 (TISCI protocol). 51 (TISCI protocol).
52 52
53 properties: 53 properties:
54 compatible: 54 compatible:
55 const: ti,sci-inta 55 const: ti,sci-inta
56 56
57 reg: 57 reg:
58 maxItems: 1 58 maxItems: 1
59 59
60 interrupt-controller: true 60 interrupt-controller: true
61 61
62 '#interrupt-cells': 62 '#interrupt-cells':
63 const: 0 63 const: 0
64 64
65 msi-controller: true 65 msi-controller: true
66 66
67 ti,interrupt-ranges: 67 ti,interrupt-ranges:
68 $ref: /schemas/types.yaml#/definitions/uin 68 $ref: /schemas/types.yaml#/definitions/uint32-matrix
69 description: | 69 description: |
70 Interrupt ranges that converts the INTA 70 Interrupt ranges that converts the INTA output hw irq numbers
71 to parents's input interrupt numbers. 71 to parents's input interrupt numbers.
72 items: 72 items:
73 items: 73 items:
74 - description: | 74 - description: |
75 "output_irq" specifies the base fo 75 "output_irq" specifies the base for inta output irq
76 - description: | 76 - description: |
77 "parent's input irq" specifies the 77 "parent's input irq" specifies the base for parent irq
78 - description: | 78 - description: |
79 "limit" specifies the limit for tr 79 "limit" specifies the limit for translation
80 80
81 ti,unmapped-event-sources: 81 ti,unmapped-event-sources:
82 $ref: /schemas/types.yaml#/definitions/pha 82 $ref: /schemas/types.yaml#/definitions/phandle-array
83 items: 83 items:
84 maxItems: 1 84 maxItems: 1
85 description: 85 description:
86 Array of phandles to DMA controllers whe 86 Array of phandles to DMA controllers where the unmapped events originate.
87 87
88 power-domains: <<
89 maxItems: 1 <<
90 <<
91 required: 88 required:
92 - compatible 89 - compatible
93 - reg 90 - reg
94 - interrupt-controller 91 - interrupt-controller
95 - msi-controller 92 - msi-controller
96 - ti,sci 93 - ti,sci
97 - ti,sci-dev-id 94 - ti,sci-dev-id
98 - ti,interrupt-ranges 95 - ti,interrupt-ranges
99 96
100 unevaluatedProperties: false 97 unevaluatedProperties: false
101 98
102 examples: 99 examples:
103 - | 100 - |
104 bus { 101 bus {
105 #address-cells = <2>; 102 #address-cells = <2>;
106 #size-cells = <2>; 103 #size-cells = <2>;
107 104
108 main_udmass_inta: msi-controller@33d00 105 main_udmass_inta: msi-controller@33d00000 {
109 compatible = "ti,sci-inta"; 106 compatible = "ti,sci-inta";
110 reg = <0x0 0x33d00000 0x0 0x100000 107 reg = <0x0 0x33d00000 0x0 0x100000>;
111 interrupt-controller; 108 interrupt-controller;
112 msi-controller; 109 msi-controller;
113 interrupt-parent = <&main_navss_in 110 interrupt-parent = <&main_navss_intr>;
114 ti,sci = <&dmsc>; 111 ti,sci = <&dmsc>;
115 ti,sci-dev-id = <179>; 112 ti,sci-dev-id = <179>;
116 ti,interrupt-ranges = <0 0 256>; 113 ti,interrupt-ranges = <0 0 256>;
117 }; 114 };
118 }; 115 };
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