1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/allwi 4 $id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Allwinner H6 IOMMU 7 title: Allwinner H6 IOMMU
8 8
9 maintainers: 9 maintainers:
10 - Chen-Yu Tsai <wens@csie.org> 10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org> 11 - Maxime Ripard <mripard@kernel.org>
12 12
13 properties: 13 properties:
14 "#iommu-cells": 14 "#iommu-cells":
15 const: 1 15 const: 1
16 description: 16 description:
17 The content of the cell is the master ID 17 The content of the cell is the master ID.
18 18
19 compatible: 19 compatible:
20 oneOf: !! 20 const: allwinner,sun50i-h6-iommu
21 - const: allwinner,sun50i-h6-iommu <<
22 - const: allwinner,sun50i-h616-iommu <<
23 - items: <<
24 - const: allwinner,sun55i-a523-iommu <<
25 - const: allwinner,sun50i-h616-iommu <<
26 21
27 reg: 22 reg:
28 maxItems: 1 23 maxItems: 1
29 24
30 interrupts: 25 interrupts:
31 maxItems: 1 26 maxItems: 1
32 27
33 clocks: 28 clocks:
34 maxItems: 1 29 maxItems: 1
35 30
36 resets: 31 resets:
37 maxItems: 1 32 maxItems: 1
38 33
39 required: 34 required:
40 - "#iommu-cells" 35 - "#iommu-cells"
41 - compatible 36 - compatible
42 - reg 37 - reg
43 - interrupts 38 - interrupts
44 - clocks 39 - clocks
45 - resets 40 - resets
46 41
47 additionalProperties: false 42 additionalProperties: false
48 43
49 examples: 44 examples:
50 - | 45 - |
51 #include <dt-bindings/interrupt-controll 46 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 #include <dt-bindings/interrupt-controll 47 #include <dt-bindings/interrupt-controller/irq.h>
53 48
54 #include <dt-bindings/clock/sun50i-h6-cc 49 #include <dt-bindings/clock/sun50i-h6-ccu.h>
55 #include <dt-bindings/reset/sun50i-h6-cc 50 #include <dt-bindings/reset/sun50i-h6-ccu.h>
56 51
57 iommu: iommu@30f0000 { 52 iommu: iommu@30f0000 {
58 compatible = "allwinner,sun50i-h6-io 53 compatible = "allwinner,sun50i-h6-iommu";
59 reg = <0x030f0000 0x10000>; 54 reg = <0x030f0000 0x10000>;
60 interrupts = <GIC_SPI 57 IRQ_TYPE_LE 55 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
61 clocks = <&ccu CLK_BUS_IOMMU>; 56 clocks = <&ccu CLK_BUS_IOMMU>;
62 resets = <&ccu RST_BUS_IOMMU>; 57 resets = <&ccu RST_BUS_IOMMU>;
63 #iommu-cells = <1>; 58 #iommu-cells = <1>;
64 }; 59 };
65 60
66 ... 61 ...
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