1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,s 4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM System MMU Architecture Implementat 7 title: ARM System MMU Architecture Implementation
8 8
9 maintainers: 9 maintainers:
10 - Will Deacon <will@kernel.org> 10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com> 11 - Robin Murphy <Robin.Murphy@arm.com>
12 12
13 description: |+ 13 description: |+
14 ARM SoCs may contain an implementation of th 14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be u 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters extern 16 of address translation to bus masters external to the CPU.
17 17
18 The SMMU may also raise interrupts in respon 18 The SMMU may also raise interrupts in response to various fault
19 conditions. 19 conditions.
20 20
21 properties: 21 properties:
22 $nodename: 22 $nodename:
23 pattern: "^iommu@[0-9a-f]*" 23 pattern: "^iommu@[0-9a-f]*"
24 compatible: 24 compatible:
25 oneOf: 25 oneOf:
26 - description: Qcom SoCs implementing "a 26 - description: Qcom SoCs implementing "arm,smmu-v2"
27 items: 27 items:
28 - enum: 28 - enum:
29 - qcom,msm8996-smmu-v2 29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2 30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2 <<
32 - qcom,sm6375-smmu-v2 <<
33 - const: qcom,smmu-v2 31 - const: qcom,smmu-v2
34 32
35 - description: Qcom SoCs implementing "q !! 33 - description: Qcom SoCs implementing "arm,mmu-500"
36 items: 34 items:
37 - enum: 35 - enum:
38 - qcom,qcm2290-smmu-500 <<
39 - qcom,qcs8300-smmu-500 <<
40 - qcom,qdu1000-smmu-500 <<
41 - qcom,sa8255p-smmu-500 <<
42 - qcom,sa8775p-smmu-500 <<
43 - qcom,sc7180-smmu-500 36 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500 <<
45 - qcom,sc8180x-smmu-500 37 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500 <<
47 - qcom,sdm670-smmu-500 <<
48 - qcom,sdm845-smmu-500 38 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500 <<
50 - qcom,sdx65-smmu-500 <<
51 - qcom,sdx75-smmu-500 <<
52 - qcom,sm6115-smmu-500 <<
53 - qcom,sm6125-smmu-500 <<
54 - qcom,sm6350-smmu-500 <<
55 - qcom,sm6375-smmu-500 <<
56 - qcom,sm8150-smmu-500 39 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500 40 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500 41 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500 <<
60 - qcom,sm8550-smmu-500 <<
61 - qcom,sm8650-smmu-500 <<
62 - qcom,x1e80100-smmu-500 <<
63 - const: qcom,smmu-500 <<
64 - const: arm,mmu-500 <<
65 <<
66 - description: Qcom SoCs implementing "a <<
67 deprecated: true <<
68 items: <<
69 # Do not add additional SoC to this <<
70 - enum: <<
71 - qcom,qcm2290-smmu-500 <<
72 - qcom,sc7180-smmu-500 <<
73 - qcom,sc7280-smmu-500 <<
74 - qcom,sc8180x-smmu-500 <<
75 - qcom,sc8280xp-smmu-500 <<
76 - qcom,sdm845-smmu-500 <<
77 - qcom,sm6115-smmu-500 <<
78 - qcom,sm6350-smmu-500 <<
79 - qcom,sm6375-smmu-500 <<
80 - qcom,sm8150-smmu-500 <<
81 - qcom,sm8250-smmu-500 <<
82 - qcom,sm8350-smmu-500 <<
83 - qcom,sm8450-smmu-500 <<
84 - const: arm,mmu-500 <<
85 - description: Qcom Adreno GPUs implemen <<
86 items: <<
87 - enum: <<
88 - qcom,qcm2290-smmu-500 <<
89 - qcom,sa8255p-smmu-500 <<
90 - qcom,sa8775p-smmu-500 <<
91 - qcom,sc7280-smmu-500 <<
92 - qcom,sc8180x-smmu-500 <<
93 - qcom,sc8280xp-smmu-500 <<
94 - qcom,sm6115-smmu-500 <<
95 - qcom,sm6125-smmu-500 <<
96 - qcom,sm8150-smmu-500 <<
97 - qcom,sm8250-smmu-500 <<
98 - qcom,sm8350-smmu-500 <<
99 - qcom,sm8450-smmu-500 <<
100 - qcom,sm8550-smmu-500 <<
101 - qcom,sm8650-smmu-500 <<
102 - qcom,x1e80100-smmu-500 <<
103 - const: qcom,adreno-smmu <<
104 - const: qcom,smmu-500 <<
105 - const: arm,mmu-500 <<
106 - description: Qcom Adreno GPUs implemen <<
107 deprecated: true <<
108 items: <<
109 # Do not add additional SoC to this <<
110 - enum: <<
111 - qcom,sc7280-smmu-500 <<
112 - qcom,sm8150-smmu-500 <<
113 - qcom,sm8250-smmu-500 <<
114 - const: qcom,adreno-smmu <<
115 - const: arm,mmu-500 42 - const: arm,mmu-500
116 - description: Qcom Adreno GPUs implemen 43 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
117 items: 44 items:
118 - enum: 45 - enum:
119 - qcom,msm8996-smmu-v2 <<
120 - qcom,sc7180-smmu-v2 46 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2 <<
122 - qcom,sdm845-smmu-v2 47 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2 <<
124 - qcom,sm7150-smmu-v2 <<
125 - const: qcom,adreno-smmu 48 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2 49 - const: qcom,smmu-v2
127 - description: Qcom Adreno GPUs on Googl <<
128 items: <<
129 - const: qcom,sdm845-smmu-v2 <<
130 - const: qcom,smmu-v2 <<
131 - description: Marvell SoCs implementing 50 - description: Marvell SoCs implementing "arm,mmu-500"
132 items: 51 items:
133 - const: marvell,ap806-smmu-500 52 - const: marvell,ap806-smmu-500
134 - const: arm,mmu-500 53 - const: arm,mmu-500
135 - description: NVIDIA SoCs that require !! 54 - description: NVIDIA SoCs that program two ARM MMU-500s identically
136 and may program multiple ARM MMU-500 <<
137 controller interleaving translations <<
138 for improved performance. <<
139 items: 55 items:
140 - enum: 56 - enum:
141 - nvidia,tegra186-smmu <<
142 - nvidia,tegra194-smmu 57 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu <<
144 - const: nvidia,smmu-500 58 - const: nvidia,smmu-500
145 - items: 59 - items:
146 - const: arm,mmu-500 60 - const: arm,mmu-500
147 - const: arm,smmu-v2 61 - const: arm,smmu-v2
148 - items: 62 - items:
149 - enum: 63 - enum:
150 - arm,mmu-400 64 - arm,mmu-400
151 - arm,mmu-401 65 - arm,mmu-401
152 - const: arm,smmu-v1 66 - const: arm,smmu-v1
153 - enum: 67 - enum:
154 - arm,smmu-v1 68 - arm,smmu-v1
155 - arm,smmu-v2 69 - arm,smmu-v2
156 - arm,mmu-400 70 - arm,mmu-400
157 - arm,mmu-401 71 - arm,mmu-401
158 - arm,mmu-500 72 - arm,mmu-500
159 - cavium,smmu-v2 73 - cavium,smmu-v2
160 74
161 reg: 75 reg:
162 minItems: 1 76 minItems: 1
163 maxItems: 2 77 maxItems: 2
164 78
165 '#global-interrupts': 79 '#global-interrupts':
166 description: The number of global interrup 80 description: The number of global interrupts exposed by the device.
167 $ref: /schemas/types.yaml#/definitions/uin 81 $ref: /schemas/types.yaml#/definitions/uint32
168 minimum: 0 82 minimum: 0
169 maximum: 260 # 2 secure, 2 non-secure, a 83 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
170 84
171 '#iommu-cells': 85 '#iommu-cells':
172 enum: [ 1, 2 ] 86 enum: [ 1, 2 ]
173 description: | 87 description: |
174 See Documentation/devicetree/bindings/io 88 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
175 value of 1, each IOMMU specifier represe 89 value of 1, each IOMMU specifier represents a distinct stream ID emitted
176 by that device into the relevant SMMU. 90 by that device into the relevant SMMU.
177 91
178 SMMUs with stream matching support and c 92 SMMUs with stream matching support and complex masters may use a value of
179 2, where the second cell of the IOMMU sp 93 2, where the second cell of the IOMMU specifier represents an SMR mask to
180 combine with the ID in the first cell. 94 combine with the ID in the first cell. Care must be taken to ensure the
181 set of matched IDs does not result in co 95 set of matched IDs does not result in conflicts.
182 96
183 interrupts: 97 interrupts:
184 minItems: 1 98 minItems: 1
185 maxItems: 388 # 260 plus 128 contexts 99 maxItems: 388 # 260 plus 128 contexts
186 description: | 100 description: |
187 Interrupt list, with the first #global-i 101 Interrupt list, with the first #global-interrupts entries corresponding to
188 the global interrupts and any following 102 the global interrupts and any following entries corresponding to context
189 interrupts, specified in order of their 103 interrupts, specified in order of their indexing by the SMMU.
190 104
191 For SMMUv2 implementations, there must b 105 For SMMUv2 implementations, there must be exactly one interrupt per
192 context bank. In the case of a single, c 106 context bank. In the case of a single, combined interrupt, it must be
193 listed multiple times. 107 listed multiple times.
194 108
195 dma-coherent: 109 dma-coherent:
196 description: | 110 description: |
197 Present if page table walks made by the 111 Present if page table walks made by the SMMU are cache coherent with the
198 CPU. 112 CPU.
199 113
200 NOTE: this only applies to the SMMU itse 114 NOTE: this only applies to the SMMU itself, not masters connected
201 upstream of the SMMU. 115 upstream of the SMMU.
202 116
203 calxeda,smmu-secure-config-access: 117 calxeda,smmu-secure-config-access:
204 type: boolean 118 type: boolean
205 description: 119 description:
206 Enable proper handling of buggy implemen 120 Enable proper handling of buggy implementations that always use secure
207 access to SMMU configuration registers. 121 access to SMMU configuration registers. In this case non-secure aliases of
208 secure registers have to be used during 122 secure registers have to be used during SMMU configuration.
209 123
210 stream-match-mask: 124 stream-match-mask:
211 $ref: /schemas/types.yaml#/definitions/uin 125 $ref: /schemas/types.yaml#/definitions/uint32
212 description: | 126 description: |
213 For SMMUs supporting stream matching and 127 For SMMUs supporting stream matching and using #iommu-cells = <1>,
214 specifies a mask of bits to ignore when 128 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
215 be programmed into the SMRn.MASK field o 129 be programmed into the SMRn.MASK field of every stream match register
216 used). For cases where it is desirable t 130 used). For cases where it is desirable to ignore some portion of every
217 Stream ID (e.g. for certain MMU-500 conf 131 Stream ID (e.g. for certain MMU-500 configurations given globally unique
218 input IDs). This property is not valid f 132 input IDs). This property is not valid for SMMUs using stream indexing, or
219 using stream matching with #iommu-cells 133 using stream matching with #iommu-cells = <2>, and may be ignored if
220 present in such cases. 134 present in such cases.
221 135
222 clock-names: 136 clock-names:
223 minItems: 1 !! 137 items:
224 maxItems: 7 !! 138 - const: bus
>> 139 - const: iface
225 140
226 clocks: 141 clocks:
227 minItems: 1 !! 142 items:
228 maxItems: 7 !! 143 - description: bus clock required for downstream bus access and for the
>> 144 smmu ptw
>> 145 - description: interface clock required to access smmu's registers
>> 146 through the TCU's programming interface.
229 147
230 power-domains: 148 power-domains:
231 minItems: 1 !! 149 maxItems: 1
232 maxItems: 3 <<
233 <<
234 nvidia,memory-controller: <<
235 description: | <<
236 A phandle to the memory controller on NV <<
237 The memory controller needs to be progra <<
238 client IDs to ARM SMMU stream IDs. <<
239 <<
240 If this property is absent, the mapping <<
241 will be used and it is not guaranteed th <<
242 enabled for any given device. <<
243 $ref: /schemas/types.yaml#/definitions/pha <<
244 150
245 required: 151 required:
246 - compatible 152 - compatible
247 - reg 153 - reg
248 - '#global-interrupts' 154 - '#global-interrupts'
249 - '#iommu-cells' 155 - '#iommu-cells'
250 - interrupts 156 - interrupts
251 157
252 additionalProperties: false 158 additionalProperties: false
253 159
254 allOf: 160 allOf:
255 - if: 161 - if:
256 properties: 162 properties:
257 compatible: 163 compatible:
258 contains: 164 contains:
259 enum: 165 enum:
260 - nvidia,tegra186-smmu <<
261 - nvidia,tegra194-smmu 166 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu <<
263 then: 167 then:
264 properties: 168 properties:
265 reg: 169 reg:
266 minItems: 1 !! 170 minItems: 2
267 maxItems: 2 171 maxItems: 2
268 <<
269 # The reference to the memory controller <<
270 # memory client to stream ID mapping can <<
271 # IOMMU attachment. <<
272 required: <<
273 - nvidia,memory-controller <<
274 else: 172 else:
275 properties: 173 properties:
276 reg: 174 reg:
277 maxItems: 1 <<
278 <<
279 - if: <<
280 properties: <<
281 compatible: <<
282 contains: <<
283 enum: <<
284 - qcom,msm8998-smmu-v2 <<
285 - qcom,sdm630-smmu-v2 <<
286 then: <<
287 anyOf: <<
288 - properties: <<
289 clock-names: <<
290 items: <<
291 - const: bus <<
292 clocks: <<
293 items: <<
294 - description: bus clock requi <<
295 the smmu ptw <<
296 - properties: <<
297 clock-names: <<
298 items: <<
299 - const: iface <<
300 - const: mem <<
301 - const: mem_iface <<
302 clocks: <<
303 items: <<
304 - description: interface clock <<
305 through the TCU's programm <<
306 - description: bus clock requi <<
307 - description: bus clock requi <<
308 - properties: <<
309 clock-names: <<
310 items: <<
311 - const: iface-mm <<
312 - const: iface-smmu <<
313 - const: bus-smmu <<
314 clocks: <<
315 items: <<
316 - description: interface clock <<
317 through the TCU's programm <<
318 - description: interface clock <<
319 through the TCU's programm <<
320 - description: bus clock requi <<
321 <<
322 - if: <<
323 properties: <<
324 compatible: <<
325 contains: <<
326 enum: <<
327 - qcom,sm6375-smmu-v2 <<
328 then: <<
329 anyOf: <<
330 - properties: <<
331 clock-names: <<
332 items: <<
333 - const: bus <<
334 clocks: <<
335 items: <<
336 - description: bus clock requi <<
337 the smmu ptw <<
338 - properties: <<
339 clock-names: <<
340 items: <<
341 - const: iface <<
342 - const: mem <<
343 - const: mem_iface <<
344 clocks: <<
345 items: <<
346 - description: interface clock <<
347 through the TCU's programm <<
348 - description: bus clock requi <<
349 - description: bus clock requi <<
350 - properties: <<
351 clock-names: <<
352 items: <<
353 - const: iface-mm <<
354 - const: iface-smmu <<
355 - const: bus-mm <<
356 - const: bus-smmu <<
357 clocks: <<
358 items: <<
359 - description: interface clock <<
360 through the TCU's programm <<
361 - description: interface clock <<
362 through the TCU's programm <<
363 - description: bus clock requi <<
364 - description: bus clock requi <<
365 <<
366 - if: <<
367 properties: <<
368 compatible: <<
369 contains: <<
370 enum: <<
371 - qcom,msm8996-smmu-v2 <<
372 - qcom,sc7180-smmu-v2 <<
373 - qcom,sdm845-smmu-v2 <<
374 then: <<
375 properties: <<
376 clock-names: <<
377 items: <<
378 - const: bus <<
379 - const: iface <<
380 <<
381 clocks: <<
382 items: <<
383 - description: bus clock required <<
384 the smmu ptw <<
385 - description: interface clock req <<
386 through the TCU's programming <<
387 <<
388 - if: <<
389 properties: <<
390 compatible: <<
391 contains: <<
392 enum: <<
393 - qcom,sa8775p-smmu-500 <<
394 - qcom,sc7280-smmu-500 <<
395 - qcom,sc8280xp-smmu-500 <<
396 then: <<
397 properties: <<
398 clock-names: <<
399 items: <<
400 - const: gcc_gpu_memnoc_gfx_clk <<
401 - const: gcc_gpu_snoc_dvm_gfx_clk <<
402 - const: gpu_cc_ahb_clk <<
403 - const: gpu_cc_hlos1_vote_gpu_smm <<
404 - const: gpu_cc_cx_gmu_clk <<
405 - const: gpu_cc_hub_cx_int_clk <<
406 - const: gpu_cc_hub_aon_clk <<
407 <<
408 clocks: <<
409 items: <<
410 - description: GPU memnoc_gfx cloc <<
411 - description: GPU snoc_dvm_gfx cl <<
412 - description: GPU ahb clock <<
413 - description: GPU hlos1_vote_GPU <<
414 - description: GPU cx_gmu clock <<
415 - description: GPU hub_cx_int cloc <<
416 - description: GPU hub_aon clock <<
417 <<
418 - if: <<
419 properties: <<
420 compatible: <<
421 contains: <<
422 enum: <<
423 - qcom,sc8180x-smmu-500 <<
424 - qcom,sm6350-smmu-v2 <<
425 - qcom,sm7150-smmu-v2 <<
426 - qcom,sm8150-smmu-500 <<
427 - qcom,sm8250-smmu-500 <<
428 then: <<
429 properties: <<
430 clock-names: <<
431 items: <<
432 - const: ahb <<
433 - const: bus <<
434 - const: iface <<
435 <<
436 clocks: <<
437 items: <<
438 - description: bus clock required <<
439 - description: bus clock required <<
440 the smmu ptw <<
441 - description: interface clock req <<
442 through the TCU's programming <<
443 <<
444 - if: <<
445 properties: <<
446 compatible: <<
447 items: <<
448 - enum: <<
449 - qcom,sm8350-smmu-500 <<
450 - const: qcom,adreno-smmu <<
451 - const: qcom,smmu-500 <<
452 - const: arm,mmu-500 <<
453 then: <<
454 properties: <<
455 clock-names: <<
456 items: <<
457 - const: bus <<
458 - const: iface <<
459 - const: ahb <<
460 - const: hlos1_vote_gpu_smmu <<
461 - const: cx_gmu <<
462 - const: hub_cx_int <<
463 - const: hub_aon <<
464 clocks: <<
465 minItems: 7 <<
466 maxItems: 7 <<
467 <<
468 - if: <<
469 properties: <<
470 compatible: <<
471 items: <<
472 - enum: <<
473 - qcom,qcm2290-smmu-500 <<
474 - qcom,sm6115-smmu-500 <<
475 - qcom,sm6125-smmu-500 <<
476 - const: qcom,adreno-smmu <<
477 - const: qcom,smmu-500 <<
478 - const: arm,mmu-500 <<
479 then: <<
480 properties: <<
481 clock-names: <<
482 items: <<
483 - const: mem <<
484 - const: hlos <<
485 - const: iface <<
486 <<
487 clocks: <<
488 items: <<
489 - description: GPU memory bus cloc <<
490 - description: Voter clock require <<
491 - description: Interface clock req <<
492 <<
493 - if: <<
494 properties: <<
495 compatible: <<
496 items: <<
497 - const: qcom,sm8450-smmu-500 <<
498 - const: qcom,adreno-smmu <<
499 - const: qcom,smmu-500 <<
500 - const: arm,mmu-500 <<
501 <<
502 then: <<
503 properties: <<
504 clock-names: <<
505 items: <<
506 - const: gmu <<
507 - const: hub <<
508 - const: hlos <<
509 - const: bus <<
510 - const: iface <<
511 - const: ahb <<
512 <<
513 clocks: <<
514 items: <<
515 - description: GMU clock <<
516 - description: GPU HUB clock <<
517 - description: HLOS vote clock <<
518 - description: GPU memory bus cloc <<
519 - description: GPU SNoC bus clock <<
520 - description: GPU AHB clock <<
521 <<
522 - if: <<
523 properties: <<
524 compatible: <<
525 items: <<
526 - enum: <<
527 - qcom,sm8550-smmu-500 <<
528 - qcom,sm8650-smmu-500 <<
529 - qcom,x1e80100-smmu-500 <<
530 - const: qcom,adreno-smmu <<
531 - const: qcom,smmu-500 <<
532 - const: arm,mmu-500 <<
533 then: <<
534 properties: <<
535 clock-names: <<
536 items: <<
537 - const: hlos <<
538 - const: bus <<
539 - const: iface <<
540 - const: ahb <<
541 <<
542 clocks: <<
543 items: <<
544 - description: HLOS vote clock <<
545 - description: GPU memory bus cloc <<
546 - description: GPU SNoC bus clock <<
547 - description: GPU AHB clock <<
548 <<
549 # Disallow clocks for all other platforms wi <<
550 - if: <<
551 properties: <<
552 compatible: <<
553 contains: <<
554 enum: <<
555 - cavium,smmu-v2 <<
556 - marvell,ap806-smmu-500 <<
557 - nvidia,smmu-500 <<
558 - qcom,qcs8300-smmu-500 <<
559 - qcom,qdu1000-smmu-500 <<
560 - qcom,sa8255p-smmu-500 <<
561 - qcom,sc7180-smmu-500 <<
562 - qcom,sdm670-smmu-500 <<
563 - qcom,sdm845-smmu-500 <<
564 - qcom,sdx55-smmu-500 <<
565 - qcom,sdx65-smmu-500 <<
566 - qcom,sm6350-smmu-500 <<
567 - qcom,sm6375-smmu-500 <<
568 then: <<
569 properties: <<
570 clock-names: false <<
571 clocks: false <<
572 <<
573 - if: <<
574 properties: <<
575 compatible: <<
576 contains: <<
577 const: qcom,sm6375-smmu-500 <<
578 then: <<
579 properties: <<
580 power-domains: <<
581 items: <<
582 - description: SNoC MMU TBU RT GDS <<
583 - description: SNoC MMU TBU NRT GD <<
584 - description: SNoC TURING MMU TBU <<
585 <<
586 required: <<
587 - power-domains <<
588 else: <<
589 properties: <<
590 power-domains: <<
591 maxItems: 1 175 maxItems: 1
592 176
593 examples: 177 examples:
594 - |+ 178 - |+
595 /* SMMU with stream matching or stream ind 179 /* SMMU with stream matching or stream indexing */
596 smmu1: iommu@ba5e0000 { 180 smmu1: iommu@ba5e0000 {
597 compatible = "arm,smmu-v1"; 181 compatible = "arm,smmu-v1";
598 reg = <0xba5e0000 0x10000>; 182 reg = <0xba5e0000 0x10000>;
599 #global-interrupts = <2>; 183 #global-interrupts = <2>;
600 interrupts = <0 32 4>, 184 interrupts = <0 32 4>,
601 <0 33 4>, 185 <0 33 4>,
602 <0 34 4>, /* This is 186 <0 34 4>, /* This is the first context interrupt */
603 <0 35 4>, 187 <0 35 4>,
604 <0 36 4>, 188 <0 36 4>,
605 <0 37 4>; 189 <0 37 4>;
606 #iommu-cells = <1>; 190 #iommu-cells = <1>;
607 }; 191 };
608 192
609 /* device with two stream IDs, 0 and 7 */ 193 /* device with two stream IDs, 0 and 7 */
610 master1 { 194 master1 {
611 iommus = <&smmu1 0>, 195 iommus = <&smmu1 0>,
612 <&smmu1 7>; 196 <&smmu1 7>;
613 }; 197 };
614 198
615 199
616 /* SMMU with stream matching */ 200 /* SMMU with stream matching */
617 smmu2: iommu@ba5f0000 { 201 smmu2: iommu@ba5f0000 {
618 compatible = "arm,smmu-v1"; 202 compatible = "arm,smmu-v1";
619 reg = <0xba5f0000 0x10000>; 203 reg = <0xba5f0000 0x10000>;
620 #global-interrupts = <2>; 204 #global-interrupts = <2>;
621 interrupts = <0 38 4>, 205 interrupts = <0 38 4>,
622 <0 39 4>, 206 <0 39 4>,
623 <0 40 4>, /* This is 207 <0 40 4>, /* This is the first context interrupt */
624 <0 41 4>, 208 <0 41 4>,
625 <0 42 4>, 209 <0 42 4>,
626 <0 43 4>; 210 <0 43 4>;
627 #iommu-cells = <2>; 211 #iommu-cells = <2>;
628 }; 212 };
629 213
630 /* device with stream IDs 0 and 7 */ 214 /* device with stream IDs 0 and 7 */
631 master2 { 215 master2 {
632 iommus = <&smmu2 0 0>, 216 iommus = <&smmu2 0 0>,
633 <&smmu2 7 0>; 217 <&smmu2 7 0>;
634 }; 218 };
635 219
636 /* device with stream IDs 1, 17, 33 and 49 220 /* device with stream IDs 1, 17, 33 and 49 */
637 master3 { 221 master3 {
638 iommus = <&smmu2 1 0x30>; 222 iommus = <&smmu2 1 0x30>;
639 }; 223 };
640 224
641 225
642 /* ARM MMU-500 with 10-bit stream ID input 226 /* ARM MMU-500 with 10-bit stream ID input configuration */
643 smmu3: iommu@ba600000 { 227 smmu3: iommu@ba600000 {
644 compatible = "arm,mmu-500", "arm,s 228 compatible = "arm,mmu-500", "arm,smmu-v2";
645 reg = <0xba600000 0x10000>; 229 reg = <0xba600000 0x10000>;
646 #global-interrupts = <2>; 230 #global-interrupts = <2>;
647 interrupts = <0 44 4>, 231 interrupts = <0 44 4>,
648 <0 45 4>, 232 <0 45 4>,
649 <0 46 4>, /* This is 233 <0 46 4>, /* This is the first context interrupt */
650 <0 47 4>, 234 <0 47 4>,
651 <0 48 4>, 235 <0 48 4>,
652 <0 49 4>; 236 <0 49 4>;
653 #iommu-cells = <1>; 237 #iommu-cells = <1>;
654 /* always ignore appended 5-bit TB 238 /* always ignore appended 5-bit TBU number */
655 stream-match-mask = <0x7c00>; 239 stream-match-mask = <0x7c00>;
656 }; 240 };
657 241
658 bus { 242 bus {
659 /* bus whose child devices emit on 243 /* bus whose child devices emit one unique 10-bit stream
660 ID each, but may master through 244 ID each, but may master through multiple SMMU TBUs */
661 iommu-map = <0 &smmu3 0 0x400>; 245 iommu-map = <0 &smmu3 0 0x400>;
662 246
663 247
664 }; 248 };
665 249
666 - |+ 250 - |+
667 /* Qcom's arm,smmu-v2 implementation */ 251 /* Qcom's arm,smmu-v2 implementation */
668 #include <dt-bindings/interrupt-controller 252 #include <dt-bindings/interrupt-controller/arm-gic.h>
669 #include <dt-bindings/interrupt-controller 253 #include <dt-bindings/interrupt-controller/irq.h>
670 smmu4: iommu@d00000 { 254 smmu4: iommu@d00000 {
671 compatible = "qcom,msm8996-smmu-v2", "qc 255 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
672 reg = <0xd00000 0x10000>; 256 reg = <0xd00000 0x10000>;
673 257
674 #global-interrupts = <1>; 258 #global-interrupts = <1>;
675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_ 259 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH> 260 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH> 261 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
678 #iommu-cells = <1>; 262 #iommu-cells = <1>;
679 power-domains = <&mmcc 0>; 263 power-domains = <&mmcc 0>;
680 264
681 clocks = <&mmcc 123>, 265 clocks = <&mmcc 123>,
682 <&mmcc 124>; 266 <&mmcc 124>;
683 clock-names = "bus", "iface"; 267 clock-names = "bus", "iface";
684 }; 268 };
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