1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,s 4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM System MMU Architecture Implementat 7 title: ARM System MMU Architecture Implementation
8 8
9 maintainers: 9 maintainers:
10 - Will Deacon <will@kernel.org> 10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com> 11 - Robin Murphy <Robin.Murphy@arm.com>
12 12
13 description: |+ 13 description: |+
14 ARM SoCs may contain an implementation of th 14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be u 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters extern 16 of address translation to bus masters external to the CPU.
17 17
18 The SMMU may also raise interrupts in respon 18 The SMMU may also raise interrupts in response to various fault
19 conditions. 19 conditions.
20 20
21 properties: 21 properties:
22 $nodename: 22 $nodename:
23 pattern: "^iommu@[0-9a-f]*" 23 pattern: "^iommu@[0-9a-f]*"
24 compatible: 24 compatible:
25 oneOf: 25 oneOf:
26 - description: Qcom SoCs implementing "a 26 - description: Qcom SoCs implementing "arm,smmu-v2"
27 items: 27 items:
28 - enum: 28 - enum:
29 - qcom,msm8996-smmu-v2 29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2 30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2 31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2 32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2 33 - const: qcom,smmu-v2
34 34
35 - description: Qcom SoCs implementing "q 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36 items: 36 items:
37 - enum: 37 - enum:
38 - qcom,qcm2290-smmu-500 38 - qcom,qcm2290-smmu-500
39 - qcom,qcs8300-smmu-500 <<
40 - qcom,qdu1000-smmu-500 39 - qcom,qdu1000-smmu-500
41 - qcom,sa8255p-smmu-500 <<
42 - qcom,sa8775p-smmu-500 40 - qcom,sa8775p-smmu-500
43 - qcom,sc7180-smmu-500 41 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500 42 - qcom,sc7280-smmu-500
45 - qcom,sc8180x-smmu-500 43 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500 44 - qcom,sc8280xp-smmu-500
47 - qcom,sdm670-smmu-500 45 - qcom,sdm670-smmu-500
48 - qcom,sdm845-smmu-500 46 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500 47 - qcom,sdx55-smmu-500
50 - qcom,sdx65-smmu-500 48 - qcom,sdx65-smmu-500
51 - qcom,sdx75-smmu-500 49 - qcom,sdx75-smmu-500
52 - qcom,sm6115-smmu-500 50 - qcom,sm6115-smmu-500
53 - qcom,sm6125-smmu-500 51 - qcom,sm6125-smmu-500
54 - qcom,sm6350-smmu-500 52 - qcom,sm6350-smmu-500
55 - qcom,sm6375-smmu-500 53 - qcom,sm6375-smmu-500
56 - qcom,sm8150-smmu-500 54 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500 55 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500 56 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500 57 - qcom,sm8450-smmu-500
60 - qcom,sm8550-smmu-500 58 - qcom,sm8550-smmu-500
61 - qcom,sm8650-smmu-500 59 - qcom,sm8650-smmu-500
62 - qcom,x1e80100-smmu-500 60 - qcom,x1e80100-smmu-500
63 - const: qcom,smmu-500 61 - const: qcom,smmu-500
64 - const: arm,mmu-500 62 - const: arm,mmu-500
65 63
66 - description: Qcom SoCs implementing "a 64 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
67 deprecated: true 65 deprecated: true
68 items: 66 items:
69 # Do not add additional SoC to this 67 # Do not add additional SoC to this list. Instead use two previous lists.
70 - enum: 68 - enum:
71 - qcom,qcm2290-smmu-500 69 - qcom,qcm2290-smmu-500
72 - qcom,sc7180-smmu-500 70 - qcom,sc7180-smmu-500
73 - qcom,sc7280-smmu-500 71 - qcom,sc7280-smmu-500
74 - qcom,sc8180x-smmu-500 72 - qcom,sc8180x-smmu-500
75 - qcom,sc8280xp-smmu-500 73 - qcom,sc8280xp-smmu-500
76 - qcom,sdm845-smmu-500 74 - qcom,sdm845-smmu-500
77 - qcom,sm6115-smmu-500 75 - qcom,sm6115-smmu-500
78 - qcom,sm6350-smmu-500 76 - qcom,sm6350-smmu-500
79 - qcom,sm6375-smmu-500 77 - qcom,sm6375-smmu-500
80 - qcom,sm8150-smmu-500 78 - qcom,sm8150-smmu-500
81 - qcom,sm8250-smmu-500 79 - qcom,sm8250-smmu-500
82 - qcom,sm8350-smmu-500 80 - qcom,sm8350-smmu-500
83 - qcom,sm8450-smmu-500 81 - qcom,sm8450-smmu-500
84 - const: arm,mmu-500 82 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implemen 83 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
86 items: 84 items:
87 - enum: 85 - enum:
88 - qcom,qcm2290-smmu-500 86 - qcom,qcm2290-smmu-500
89 - qcom,sa8255p-smmu-500 <<
90 - qcom,sa8775p-smmu-500 87 - qcom,sa8775p-smmu-500
91 - qcom,sc7280-smmu-500 88 - qcom,sc7280-smmu-500
92 - qcom,sc8180x-smmu-500 <<
93 - qcom,sc8280xp-smmu-500 89 - qcom,sc8280xp-smmu-500
94 - qcom,sm6115-smmu-500 90 - qcom,sm6115-smmu-500
95 - qcom,sm6125-smmu-500 91 - qcom,sm6125-smmu-500
96 - qcom,sm8150-smmu-500 92 - qcom,sm8150-smmu-500
97 - qcom,sm8250-smmu-500 93 - qcom,sm8250-smmu-500
98 - qcom,sm8350-smmu-500 94 - qcom,sm8350-smmu-500
99 - qcom,sm8450-smmu-500 95 - qcom,sm8450-smmu-500
100 - qcom,sm8550-smmu-500 96 - qcom,sm8550-smmu-500
101 - qcom,sm8650-smmu-500 97 - qcom,sm8650-smmu-500
102 - qcom,x1e80100-smmu-500 <<
103 - const: qcom,adreno-smmu 98 - const: qcom,adreno-smmu
104 - const: qcom,smmu-500 99 - const: qcom,smmu-500
105 - const: arm,mmu-500 100 - const: arm,mmu-500
106 - description: Qcom Adreno GPUs implemen 101 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
107 deprecated: true 102 deprecated: true
108 items: 103 items:
109 # Do not add additional SoC to this 104 # Do not add additional SoC to this list. Instead use previous list.
110 - enum: 105 - enum:
111 - qcom,sc7280-smmu-500 106 - qcom,sc7280-smmu-500
112 - qcom,sm8150-smmu-500 107 - qcom,sm8150-smmu-500
113 - qcom,sm8250-smmu-500 108 - qcom,sm8250-smmu-500
114 - const: qcom,adreno-smmu 109 - const: qcom,adreno-smmu
115 - const: arm,mmu-500 110 - const: arm,mmu-500
116 - description: Qcom Adreno GPUs implemen 111 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
117 items: 112 items:
118 - enum: 113 - enum:
119 - qcom,msm8996-smmu-v2 114 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2 115 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2 116 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2 117 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2 118 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2 119 - qcom,sm7150-smmu-v2
125 - const: qcom,adreno-smmu 120 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2 121 - const: qcom,smmu-v2
127 - description: Qcom Adreno GPUs on Googl 122 - description: Qcom Adreno GPUs on Google Cheza platform
128 items: 123 items:
129 - const: qcom,sdm845-smmu-v2 124 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2 125 - const: qcom,smmu-v2
131 - description: Marvell SoCs implementing 126 - description: Marvell SoCs implementing "arm,mmu-500"
132 items: 127 items:
133 - const: marvell,ap806-smmu-500 128 - const: marvell,ap806-smmu-500
134 - const: arm,mmu-500 129 - const: arm,mmu-500
135 - description: NVIDIA SoCs that require 130 - description: NVIDIA SoCs that require memory controller interaction
136 and may program multiple ARM MMU-500 131 and may program multiple ARM MMU-500s identically with the memory
137 controller interleaving translations 132 controller interleaving translations between multiple instances
138 for improved performance. 133 for improved performance.
139 items: 134 items:
140 - enum: 135 - enum:
141 - nvidia,tegra186-smmu 136 - nvidia,tegra186-smmu
142 - nvidia,tegra194-smmu 137 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu 138 - nvidia,tegra234-smmu
144 - const: nvidia,smmu-500 139 - const: nvidia,smmu-500
145 - items: 140 - items:
146 - const: arm,mmu-500 141 - const: arm,mmu-500
147 - const: arm,smmu-v2 142 - const: arm,smmu-v2
148 - items: 143 - items:
149 - enum: 144 - enum:
150 - arm,mmu-400 145 - arm,mmu-400
151 - arm,mmu-401 146 - arm,mmu-401
152 - const: arm,smmu-v1 147 - const: arm,smmu-v1
153 - enum: 148 - enum:
154 - arm,smmu-v1 149 - arm,smmu-v1
155 - arm,smmu-v2 150 - arm,smmu-v2
156 - arm,mmu-400 151 - arm,mmu-400
157 - arm,mmu-401 152 - arm,mmu-401
158 - arm,mmu-500 153 - arm,mmu-500
159 - cavium,smmu-v2 154 - cavium,smmu-v2
160 155
161 reg: 156 reg:
162 minItems: 1 157 minItems: 1
163 maxItems: 2 158 maxItems: 2
164 159
165 '#global-interrupts': 160 '#global-interrupts':
166 description: The number of global interrup 161 description: The number of global interrupts exposed by the device.
167 $ref: /schemas/types.yaml#/definitions/uin 162 $ref: /schemas/types.yaml#/definitions/uint32
168 minimum: 0 163 minimum: 0
169 maximum: 260 # 2 secure, 2 non-secure, a 164 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
170 165
171 '#iommu-cells': 166 '#iommu-cells':
172 enum: [ 1, 2 ] 167 enum: [ 1, 2 ]
173 description: | 168 description: |
174 See Documentation/devicetree/bindings/io 169 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
175 value of 1, each IOMMU specifier represe 170 value of 1, each IOMMU specifier represents a distinct stream ID emitted
176 by that device into the relevant SMMU. 171 by that device into the relevant SMMU.
177 172
178 SMMUs with stream matching support and c 173 SMMUs with stream matching support and complex masters may use a value of
179 2, where the second cell of the IOMMU sp 174 2, where the second cell of the IOMMU specifier represents an SMR mask to
180 combine with the ID in the first cell. 175 combine with the ID in the first cell. Care must be taken to ensure the
181 set of matched IDs does not result in co 176 set of matched IDs does not result in conflicts.
182 177
183 interrupts: 178 interrupts:
184 minItems: 1 179 minItems: 1
185 maxItems: 388 # 260 plus 128 contexts 180 maxItems: 388 # 260 plus 128 contexts
186 description: | 181 description: |
187 Interrupt list, with the first #global-i 182 Interrupt list, with the first #global-interrupts entries corresponding to
188 the global interrupts and any following 183 the global interrupts and any following entries corresponding to context
189 interrupts, specified in order of their 184 interrupts, specified in order of their indexing by the SMMU.
190 185
191 For SMMUv2 implementations, there must b 186 For SMMUv2 implementations, there must be exactly one interrupt per
192 context bank. In the case of a single, c 187 context bank. In the case of a single, combined interrupt, it must be
193 listed multiple times. 188 listed multiple times.
194 189
195 dma-coherent: 190 dma-coherent:
196 description: | 191 description: |
197 Present if page table walks made by the 192 Present if page table walks made by the SMMU are cache coherent with the
198 CPU. 193 CPU.
199 194
200 NOTE: this only applies to the SMMU itse 195 NOTE: this only applies to the SMMU itself, not masters connected
201 upstream of the SMMU. 196 upstream of the SMMU.
202 197
203 calxeda,smmu-secure-config-access: 198 calxeda,smmu-secure-config-access:
204 type: boolean 199 type: boolean
205 description: 200 description:
206 Enable proper handling of buggy implemen 201 Enable proper handling of buggy implementations that always use secure
207 access to SMMU configuration registers. 202 access to SMMU configuration registers. In this case non-secure aliases of
208 secure registers have to be used during 203 secure registers have to be used during SMMU configuration.
209 204
210 stream-match-mask: 205 stream-match-mask:
211 $ref: /schemas/types.yaml#/definitions/uin 206 $ref: /schemas/types.yaml#/definitions/uint32
212 description: | 207 description: |
213 For SMMUs supporting stream matching and 208 For SMMUs supporting stream matching and using #iommu-cells = <1>,
214 specifies a mask of bits to ignore when 209 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
215 be programmed into the SMRn.MASK field o 210 be programmed into the SMRn.MASK field of every stream match register
216 used). For cases where it is desirable t 211 used). For cases where it is desirable to ignore some portion of every
217 Stream ID (e.g. for certain MMU-500 conf 212 Stream ID (e.g. for certain MMU-500 configurations given globally unique
218 input IDs). This property is not valid f 213 input IDs). This property is not valid for SMMUs using stream indexing, or
219 using stream matching with #iommu-cells 214 using stream matching with #iommu-cells = <2>, and may be ignored if
220 present in such cases. 215 present in such cases.
221 216
222 clock-names: 217 clock-names:
223 minItems: 1 218 minItems: 1
224 maxItems: 7 219 maxItems: 7
225 220
226 clocks: 221 clocks:
227 minItems: 1 222 minItems: 1
228 maxItems: 7 223 maxItems: 7
229 224
230 power-domains: 225 power-domains:
231 minItems: 1 226 minItems: 1
232 maxItems: 3 227 maxItems: 3
233 228
234 nvidia,memory-controller: 229 nvidia,memory-controller:
235 description: | 230 description: |
236 A phandle to the memory controller on NV 231 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
237 The memory controller needs to be progra 232 The memory controller needs to be programmed with a mapping of memory
238 client IDs to ARM SMMU stream IDs. 233 client IDs to ARM SMMU stream IDs.
239 234
240 If this property is absent, the mapping 235 If this property is absent, the mapping programmed by early firmware
241 will be used and it is not guaranteed th 236 will be used and it is not guaranteed that IOMMU translations will be
242 enabled for any given device. 237 enabled for any given device.
243 $ref: /schemas/types.yaml#/definitions/pha 238 $ref: /schemas/types.yaml#/definitions/phandle
244 239
245 required: 240 required:
246 - compatible 241 - compatible
247 - reg 242 - reg
248 - '#global-interrupts' 243 - '#global-interrupts'
249 - '#iommu-cells' 244 - '#iommu-cells'
250 - interrupts 245 - interrupts
251 246
252 additionalProperties: false 247 additionalProperties: false
253 248
254 allOf: 249 allOf:
255 - if: 250 - if:
256 properties: 251 properties:
257 compatible: 252 compatible:
258 contains: 253 contains:
259 enum: 254 enum:
260 - nvidia,tegra186-smmu 255 - nvidia,tegra186-smmu
261 - nvidia,tegra194-smmu 256 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu 257 - nvidia,tegra234-smmu
263 then: 258 then:
264 properties: 259 properties:
265 reg: 260 reg:
266 minItems: 1 261 minItems: 1
267 maxItems: 2 262 maxItems: 2
268 263
269 # The reference to the memory controller 264 # The reference to the memory controller is required to ensure that the
270 # memory client to stream ID mapping can 265 # memory client to stream ID mapping can be done synchronously with the
271 # IOMMU attachment. 266 # IOMMU attachment.
272 required: 267 required:
273 - nvidia,memory-controller 268 - nvidia,memory-controller
274 else: 269 else:
275 properties: 270 properties:
276 reg: 271 reg:
277 maxItems: 1 272 maxItems: 1
278 273
279 - if: 274 - if:
280 properties: 275 properties:
281 compatible: 276 compatible:
282 contains: 277 contains:
283 enum: 278 enum:
284 - qcom,msm8998-smmu-v2 279 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2 280 - qcom,sdm630-smmu-v2
286 then: 281 then:
287 anyOf: 282 anyOf:
288 - properties: 283 - properties:
289 clock-names: 284 clock-names:
290 items: 285 items:
291 - const: bus 286 - const: bus
292 clocks: 287 clocks:
293 items: 288 items:
294 - description: bus clock requi 289 - description: bus clock required for downstream bus access and for
295 the smmu ptw 290 the smmu ptw
296 - properties: 291 - properties:
297 clock-names: 292 clock-names:
298 items: 293 items:
299 - const: iface 294 - const: iface
300 - const: mem 295 - const: mem
301 - const: mem_iface 296 - const: mem_iface
302 clocks: 297 clocks:
303 items: 298 items:
304 - description: interface clock 299 - description: interface clock required to access smmu's registers
305 through the TCU's programm 300 through the TCU's programming interface.
306 - description: bus clock requi 301 - description: bus clock required for memory access
307 - description: bus clock requi 302 - description: bus clock required for GPU memory access
308 - properties: 303 - properties:
309 clock-names: 304 clock-names:
310 items: 305 items:
311 - const: iface-mm 306 - const: iface-mm
312 - const: iface-smmu 307 - const: iface-smmu
313 - const: bus-smmu 308 - const: bus-smmu
314 clocks: 309 clocks:
315 items: 310 items:
316 - description: interface clock 311 - description: interface clock required to access mnoc's registers
317 through the TCU's programm 312 through the TCU's programming interface.
318 - description: interface clock 313 - description: interface clock required to access smmu's registers
319 through the TCU's programm 314 through the TCU's programming interface.
320 - description: bus clock requi 315 - description: bus clock required for the smmu ptw
321 316
322 - if: 317 - if:
323 properties: 318 properties:
324 compatible: 319 compatible:
325 contains: 320 contains:
326 enum: 321 enum:
327 - qcom,sm6375-smmu-v2 322 - qcom,sm6375-smmu-v2
328 then: 323 then:
329 anyOf: 324 anyOf:
330 - properties: 325 - properties:
331 clock-names: 326 clock-names:
332 items: 327 items:
333 - const: bus 328 - const: bus
334 clocks: 329 clocks:
335 items: 330 items:
336 - description: bus clock requi 331 - description: bus clock required for downstream bus access and for
337 the smmu ptw 332 the smmu ptw
338 - properties: 333 - properties:
339 clock-names: 334 clock-names:
340 items: 335 items:
341 - const: iface 336 - const: iface
342 - const: mem 337 - const: mem
343 - const: mem_iface 338 - const: mem_iface
344 clocks: 339 clocks:
345 items: 340 items:
346 - description: interface clock 341 - description: interface clock required to access smmu's registers
347 through the TCU's programm 342 through the TCU's programming interface.
348 - description: bus clock requi 343 - description: bus clock required for memory access
349 - description: bus clock requi 344 - description: bus clock required for GPU memory access
350 - properties: 345 - properties:
351 clock-names: 346 clock-names:
352 items: 347 items:
353 - const: iface-mm 348 - const: iface-mm
354 - const: iface-smmu 349 - const: iface-smmu
355 - const: bus-mm 350 - const: bus-mm
356 - const: bus-smmu 351 - const: bus-smmu
357 clocks: 352 clocks:
358 items: 353 items:
359 - description: interface clock 354 - description: interface clock required to access mnoc's registers
360 through the TCU's programm 355 through the TCU's programming interface.
361 - description: interface clock 356 - description: interface clock required to access smmu's registers
362 through the TCU's programm 357 through the TCU's programming interface.
363 - description: bus clock requi 358 - description: bus clock required for downstream bus access
364 - description: bus clock requi 359 - description: bus clock required for the smmu ptw
365 360
366 - if: 361 - if:
367 properties: 362 properties:
368 compatible: 363 compatible:
369 contains: 364 contains:
370 enum: 365 enum:
371 - qcom,msm8996-smmu-v2 366 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2 367 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2 368 - qcom,sdm845-smmu-v2
374 then: 369 then:
375 properties: 370 properties:
376 clock-names: 371 clock-names:
377 items: 372 items:
378 - const: bus 373 - const: bus
379 - const: iface 374 - const: iface
380 375
381 clocks: 376 clocks:
382 items: 377 items:
383 - description: bus clock required 378 - description: bus clock required for downstream bus access and for
384 the smmu ptw 379 the smmu ptw
385 - description: interface clock req 380 - description: interface clock required to access smmu's registers
386 through the TCU's programming 381 through the TCU's programming interface.
387 382
388 - if: 383 - if:
389 properties: 384 properties:
390 compatible: 385 compatible:
391 contains: 386 contains:
392 enum: 387 enum:
393 - qcom,sa8775p-smmu-500 388 - qcom,sa8775p-smmu-500
394 - qcom,sc7280-smmu-500 389 - qcom,sc7280-smmu-500
395 - qcom,sc8280xp-smmu-500 390 - qcom,sc8280xp-smmu-500
396 then: 391 then:
397 properties: 392 properties:
398 clock-names: 393 clock-names:
399 items: 394 items:
400 - const: gcc_gpu_memnoc_gfx_clk 395 - const: gcc_gpu_memnoc_gfx_clk
401 - const: gcc_gpu_snoc_dvm_gfx_clk 396 - const: gcc_gpu_snoc_dvm_gfx_clk
402 - const: gpu_cc_ahb_clk 397 - const: gpu_cc_ahb_clk
403 - const: gpu_cc_hlos1_vote_gpu_smm 398 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
404 - const: gpu_cc_cx_gmu_clk 399 - const: gpu_cc_cx_gmu_clk
405 - const: gpu_cc_hub_cx_int_clk 400 - const: gpu_cc_hub_cx_int_clk
406 - const: gpu_cc_hub_aon_clk 401 - const: gpu_cc_hub_aon_clk
407 402
408 clocks: 403 clocks:
409 items: 404 items:
410 - description: GPU memnoc_gfx cloc 405 - description: GPU memnoc_gfx clock
411 - description: GPU snoc_dvm_gfx cl 406 - description: GPU snoc_dvm_gfx clock
412 - description: GPU ahb clock 407 - description: GPU ahb clock
413 - description: GPU hlos1_vote_GPU 408 - description: GPU hlos1_vote_GPU smmu clock
414 - description: GPU cx_gmu clock 409 - description: GPU cx_gmu clock
415 - description: GPU hub_cx_int cloc 410 - description: GPU hub_cx_int clock
416 - description: GPU hub_aon clock 411 - description: GPU hub_aon clock
417 412
418 - if: 413 - if:
419 properties: 414 properties:
420 compatible: 415 compatible:
421 contains: 416 contains:
422 enum: 417 enum:
423 - qcom,sc8180x-smmu-500 <<
424 - qcom,sm6350-smmu-v2 418 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2 419 - qcom,sm7150-smmu-v2
426 - qcom,sm8150-smmu-500 420 - qcom,sm8150-smmu-500
427 - qcom,sm8250-smmu-500 421 - qcom,sm8250-smmu-500
428 then: 422 then:
429 properties: 423 properties:
430 clock-names: 424 clock-names:
431 items: 425 items:
432 - const: ahb 426 - const: ahb
433 - const: bus 427 - const: bus
434 - const: iface 428 - const: iface
435 429
436 clocks: 430 clocks:
437 items: 431 items:
438 - description: bus clock required 432 - description: bus clock required for AHB bus access
439 - description: bus clock required 433 - description: bus clock required for downstream bus access and for
440 the smmu ptw 434 the smmu ptw
441 - description: interface clock req 435 - description: interface clock required to access smmu's registers
442 through the TCU's programming 436 through the TCU's programming interface.
443 437
444 - if: 438 - if:
445 properties: 439 properties:
446 compatible: 440 compatible:
447 items: 441 items:
448 - enum: 442 - enum:
449 - qcom,sm8350-smmu-500 443 - qcom,sm8350-smmu-500
450 - const: qcom,adreno-smmu 444 - const: qcom,adreno-smmu
451 - const: qcom,smmu-500 445 - const: qcom,smmu-500
452 - const: arm,mmu-500 446 - const: arm,mmu-500
453 then: 447 then:
454 properties: 448 properties:
455 clock-names: 449 clock-names:
456 items: 450 items:
457 - const: bus 451 - const: bus
458 - const: iface 452 - const: iface
459 - const: ahb 453 - const: ahb
460 - const: hlos1_vote_gpu_smmu 454 - const: hlos1_vote_gpu_smmu
461 - const: cx_gmu 455 - const: cx_gmu
462 - const: hub_cx_int 456 - const: hub_cx_int
463 - const: hub_aon 457 - const: hub_aon
464 clocks: 458 clocks:
465 minItems: 7 459 minItems: 7
466 maxItems: 7 460 maxItems: 7
467 461
468 - if: 462 - if:
469 properties: 463 properties:
470 compatible: 464 compatible:
471 items: 465 items:
472 - enum: 466 - enum:
473 - qcom,qcm2290-smmu-500 467 - qcom,qcm2290-smmu-500
474 - qcom,sm6115-smmu-500 468 - qcom,sm6115-smmu-500
475 - qcom,sm6125-smmu-500 469 - qcom,sm6125-smmu-500
476 - const: qcom,adreno-smmu 470 - const: qcom,adreno-smmu
477 - const: qcom,smmu-500 471 - const: qcom,smmu-500
478 - const: arm,mmu-500 472 - const: arm,mmu-500
479 then: 473 then:
480 properties: 474 properties:
481 clock-names: 475 clock-names:
482 items: 476 items:
483 - const: mem 477 - const: mem
484 - const: hlos 478 - const: hlos
485 - const: iface 479 - const: iface
486 480
487 clocks: 481 clocks:
488 items: 482 items:
489 - description: GPU memory bus cloc 483 - description: GPU memory bus clock
490 - description: Voter clock require 484 - description: Voter clock required for HLOS SMMU access
491 - description: Interface clock req 485 - description: Interface clock required for register access
492 486
493 - if: 487 - if:
494 properties: 488 properties:
495 compatible: 489 compatible:
496 items: 490 items:
497 - const: qcom,sm8450-smmu-500 491 - const: qcom,sm8450-smmu-500
498 - const: qcom,adreno-smmu 492 - const: qcom,adreno-smmu
499 - const: qcom,smmu-500 493 - const: qcom,smmu-500
500 - const: arm,mmu-500 494 - const: arm,mmu-500
501 495
502 then: 496 then:
503 properties: 497 properties:
504 clock-names: 498 clock-names:
505 items: 499 items:
506 - const: gmu 500 - const: gmu
507 - const: hub 501 - const: hub
508 - const: hlos 502 - const: hlos
509 - const: bus 503 - const: bus
510 - const: iface 504 - const: iface
511 - const: ahb 505 - const: ahb
512 506
513 clocks: 507 clocks:
514 items: 508 items:
515 - description: GMU clock 509 - description: GMU clock
516 - description: GPU HUB clock 510 - description: GPU HUB clock
517 - description: HLOS vote clock 511 - description: HLOS vote clock
518 - description: GPU memory bus cloc 512 - description: GPU memory bus clock
519 - description: GPU SNoC bus clock 513 - description: GPU SNoC bus clock
520 - description: GPU AHB clock 514 - description: GPU AHB clock
521 515
522 - if: 516 - if:
523 properties: 517 properties:
524 compatible: 518 compatible:
525 items: 519 items:
526 - enum: 520 - enum:
527 - qcom,sm8550-smmu-500 521 - qcom,sm8550-smmu-500
528 - qcom,sm8650-smmu-500 522 - qcom,sm8650-smmu-500
529 - qcom,x1e80100-smmu-500 <<
530 - const: qcom,adreno-smmu 523 - const: qcom,adreno-smmu
531 - const: qcom,smmu-500 524 - const: qcom,smmu-500
532 - const: arm,mmu-500 525 - const: arm,mmu-500
533 then: 526 then:
534 properties: 527 properties:
535 clock-names: 528 clock-names:
536 items: 529 items:
537 - const: hlos 530 - const: hlos
538 - const: bus 531 - const: bus
539 - const: iface 532 - const: iface
540 - const: ahb 533 - const: ahb
541 534
542 clocks: 535 clocks:
543 items: 536 items:
544 - description: HLOS vote clock 537 - description: HLOS vote clock
545 - description: GPU memory bus cloc 538 - description: GPU memory bus clock
546 - description: GPU SNoC bus clock 539 - description: GPU SNoC bus clock
547 - description: GPU AHB clock 540 - description: GPU AHB clock
548 541
549 # Disallow clocks for all other platforms wi 542 # Disallow clocks for all other platforms with specific compatibles
550 - if: 543 - if:
551 properties: 544 properties:
552 compatible: 545 compatible:
553 contains: 546 contains:
554 enum: 547 enum:
555 - cavium,smmu-v2 548 - cavium,smmu-v2
556 - marvell,ap806-smmu-500 549 - marvell,ap806-smmu-500
557 - nvidia,smmu-500 550 - nvidia,smmu-500
558 - qcom,qcs8300-smmu-500 <<
559 - qcom,qdu1000-smmu-500 551 - qcom,qdu1000-smmu-500
560 - qcom,sa8255p-smmu-500 <<
561 - qcom,sc7180-smmu-500 552 - qcom,sc7180-smmu-500
>> 553 - qcom,sc8180x-smmu-500
562 - qcom,sdm670-smmu-500 554 - qcom,sdm670-smmu-500
563 - qcom,sdm845-smmu-500 555 - qcom,sdm845-smmu-500
564 - qcom,sdx55-smmu-500 556 - qcom,sdx55-smmu-500
565 - qcom,sdx65-smmu-500 557 - qcom,sdx65-smmu-500
566 - qcom,sm6350-smmu-500 558 - qcom,sm6350-smmu-500
567 - qcom,sm6375-smmu-500 559 - qcom,sm6375-smmu-500
>> 560 - qcom,x1e80100-smmu-500
568 then: 561 then:
569 properties: 562 properties:
570 clock-names: false 563 clock-names: false
571 clocks: false 564 clocks: false
572 565
573 - if: 566 - if:
574 properties: 567 properties:
575 compatible: 568 compatible:
576 contains: 569 contains:
577 const: qcom,sm6375-smmu-500 570 const: qcom,sm6375-smmu-500
578 then: 571 then:
579 properties: 572 properties:
580 power-domains: 573 power-domains:
581 items: 574 items:
582 - description: SNoC MMU TBU RT GDS 575 - description: SNoC MMU TBU RT GDSC
583 - description: SNoC MMU TBU NRT GD 576 - description: SNoC MMU TBU NRT GDSC
584 - description: SNoC TURING MMU TBU 577 - description: SNoC TURING MMU TBU0 GDSC
585 578
586 required: 579 required:
587 - power-domains 580 - power-domains
588 else: 581 else:
589 properties: 582 properties:
590 power-domains: 583 power-domains:
591 maxItems: 1 584 maxItems: 1
592 585
593 examples: 586 examples:
594 - |+ 587 - |+
595 /* SMMU with stream matching or stream ind 588 /* SMMU with stream matching or stream indexing */
596 smmu1: iommu@ba5e0000 { 589 smmu1: iommu@ba5e0000 {
597 compatible = "arm,smmu-v1"; 590 compatible = "arm,smmu-v1";
598 reg = <0xba5e0000 0x10000>; 591 reg = <0xba5e0000 0x10000>;
599 #global-interrupts = <2>; 592 #global-interrupts = <2>;
600 interrupts = <0 32 4>, 593 interrupts = <0 32 4>,
601 <0 33 4>, 594 <0 33 4>,
602 <0 34 4>, /* This is 595 <0 34 4>, /* This is the first context interrupt */
603 <0 35 4>, 596 <0 35 4>,
604 <0 36 4>, 597 <0 36 4>,
605 <0 37 4>; 598 <0 37 4>;
606 #iommu-cells = <1>; 599 #iommu-cells = <1>;
607 }; 600 };
608 601
609 /* device with two stream IDs, 0 and 7 */ 602 /* device with two stream IDs, 0 and 7 */
610 master1 { 603 master1 {
611 iommus = <&smmu1 0>, 604 iommus = <&smmu1 0>,
612 <&smmu1 7>; 605 <&smmu1 7>;
613 }; 606 };
614 607
615 608
616 /* SMMU with stream matching */ 609 /* SMMU with stream matching */
617 smmu2: iommu@ba5f0000 { 610 smmu2: iommu@ba5f0000 {
618 compatible = "arm,smmu-v1"; 611 compatible = "arm,smmu-v1";
619 reg = <0xba5f0000 0x10000>; 612 reg = <0xba5f0000 0x10000>;
620 #global-interrupts = <2>; 613 #global-interrupts = <2>;
621 interrupts = <0 38 4>, 614 interrupts = <0 38 4>,
622 <0 39 4>, 615 <0 39 4>,
623 <0 40 4>, /* This is 616 <0 40 4>, /* This is the first context interrupt */
624 <0 41 4>, 617 <0 41 4>,
625 <0 42 4>, 618 <0 42 4>,
626 <0 43 4>; 619 <0 43 4>;
627 #iommu-cells = <2>; 620 #iommu-cells = <2>;
628 }; 621 };
629 622
630 /* device with stream IDs 0 and 7 */ 623 /* device with stream IDs 0 and 7 */
631 master2 { 624 master2 {
632 iommus = <&smmu2 0 0>, 625 iommus = <&smmu2 0 0>,
633 <&smmu2 7 0>; 626 <&smmu2 7 0>;
634 }; 627 };
635 628
636 /* device with stream IDs 1, 17, 33 and 49 629 /* device with stream IDs 1, 17, 33 and 49 */
637 master3 { 630 master3 {
638 iommus = <&smmu2 1 0x30>; 631 iommus = <&smmu2 1 0x30>;
639 }; 632 };
640 633
641 634
642 /* ARM MMU-500 with 10-bit stream ID input 635 /* ARM MMU-500 with 10-bit stream ID input configuration */
643 smmu3: iommu@ba600000 { 636 smmu3: iommu@ba600000 {
644 compatible = "arm,mmu-500", "arm,s 637 compatible = "arm,mmu-500", "arm,smmu-v2";
645 reg = <0xba600000 0x10000>; 638 reg = <0xba600000 0x10000>;
646 #global-interrupts = <2>; 639 #global-interrupts = <2>;
647 interrupts = <0 44 4>, 640 interrupts = <0 44 4>,
648 <0 45 4>, 641 <0 45 4>,
649 <0 46 4>, /* This is 642 <0 46 4>, /* This is the first context interrupt */
650 <0 47 4>, 643 <0 47 4>,
651 <0 48 4>, 644 <0 48 4>,
652 <0 49 4>; 645 <0 49 4>;
653 #iommu-cells = <1>; 646 #iommu-cells = <1>;
654 /* always ignore appended 5-bit TB 647 /* always ignore appended 5-bit TBU number */
655 stream-match-mask = <0x7c00>; 648 stream-match-mask = <0x7c00>;
656 }; 649 };
657 650
658 bus { 651 bus {
659 /* bus whose child devices emit on 652 /* bus whose child devices emit one unique 10-bit stream
660 ID each, but may master through 653 ID each, but may master through multiple SMMU TBUs */
661 iommu-map = <0 &smmu3 0 0x400>; 654 iommu-map = <0 &smmu3 0 0x400>;
662 655
663 656
664 }; 657 };
665 658
666 - |+ 659 - |+
667 /* Qcom's arm,smmu-v2 implementation */ 660 /* Qcom's arm,smmu-v2 implementation */
668 #include <dt-bindings/interrupt-controller 661 #include <dt-bindings/interrupt-controller/arm-gic.h>
669 #include <dt-bindings/interrupt-controller 662 #include <dt-bindings/interrupt-controller/irq.h>
670 smmu4: iommu@d00000 { 663 smmu4: iommu@d00000 {
671 compatible = "qcom,msm8996-smmu-v2", "qc 664 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
672 reg = <0xd00000 0x10000>; 665 reg = <0xd00000 0x10000>;
673 666
674 #global-interrupts = <1>; 667 #global-interrupts = <1>;
675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_ 668 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH> 669 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH> 670 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
678 #iommu-cells = <1>; 671 #iommu-cells = <1>;
679 power-domains = <&mmcc 0>; 672 power-domains = <&mmcc 0>;
680 673
681 clocks = <&mmcc 123>, 674 clocks = <&mmcc 123>,
682 <&mmcc 124>; 675 <&mmcc 124>;
683 clock-names = "bus", "iface"; 676 clock-names = "bus", "iface";
684 }; 677 };
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