1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,s 4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM System MMU Architecture Implementat 7 title: ARM System MMU Architecture Implementation
8 8
9 maintainers: 9 maintainers:
10 - Will Deacon <will@kernel.org> 10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com> 11 - Robin Murphy <Robin.Murphy@arm.com>
12 12
13 description: |+ 13 description: |+
14 ARM SoCs may contain an implementation of th 14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be u 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters extern 16 of address translation to bus masters external to the CPU.
17 17
18 The SMMU may also raise interrupts in respon 18 The SMMU may also raise interrupts in response to various fault
19 conditions. 19 conditions.
20 20
21 properties: 21 properties:
22 $nodename: 22 $nodename:
23 pattern: "^iommu@[0-9a-f]*" 23 pattern: "^iommu@[0-9a-f]*"
24 compatible: 24 compatible:
25 oneOf: 25 oneOf:
26 - description: Qcom SoCs implementing "a 26 - description: Qcom SoCs implementing "arm,smmu-v2"
27 items: 27 items:
28 - enum: 28 - enum:
29 - qcom,msm8996-smmu-v2 29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2 30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2 31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2 <<
33 - const: qcom,smmu-v2 32 - const: qcom,smmu-v2
34 33
35 - description: Qcom SoCs implementing "q 34 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36 items: 35 items:
37 - enum: 36 - enum:
38 - qcom,qcm2290-smmu-500 37 - qcom,qcm2290-smmu-500
39 - qcom,qcs8300-smmu-500 <<
40 - qcom,qdu1000-smmu-500 38 - qcom,qdu1000-smmu-500
41 - qcom,sa8255p-smmu-500 <<
42 - qcom,sa8775p-smmu-500 39 - qcom,sa8775p-smmu-500
43 - qcom,sc7180-smmu-500 40 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500 41 - qcom,sc7280-smmu-500
45 - qcom,sc8180x-smmu-500 42 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500 43 - qcom,sc8280xp-smmu-500
47 - qcom,sdm670-smmu-500 44 - qcom,sdm670-smmu-500
48 - qcom,sdm845-smmu-500 45 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500 46 - qcom,sdx55-smmu-500
50 - qcom,sdx65-smmu-500 47 - qcom,sdx65-smmu-500
51 - qcom,sdx75-smmu-500 <<
52 - qcom,sm6115-smmu-500 48 - qcom,sm6115-smmu-500
53 - qcom,sm6125-smmu-500 49 - qcom,sm6125-smmu-500
54 - qcom,sm6350-smmu-500 50 - qcom,sm6350-smmu-500
55 - qcom,sm6375-smmu-500 51 - qcom,sm6375-smmu-500
56 - qcom,sm8150-smmu-500 52 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500 53 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500 54 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500 55 - qcom,sm8450-smmu-500
60 - qcom,sm8550-smmu-500 <<
61 - qcom,sm8650-smmu-500 <<
62 - qcom,x1e80100-smmu-500 <<
63 - const: qcom,smmu-500 56 - const: qcom,smmu-500
64 - const: arm,mmu-500 57 - const: arm,mmu-500
65 58
66 - description: Qcom SoCs implementing "a 59 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
67 deprecated: true 60 deprecated: true
68 items: 61 items:
69 # Do not add additional SoC to this 62 # Do not add additional SoC to this list. Instead use two previous lists.
70 - enum: 63 - enum:
71 - qcom,qcm2290-smmu-500 64 - qcom,qcm2290-smmu-500
72 - qcom,sc7180-smmu-500 65 - qcom,sc7180-smmu-500
73 - qcom,sc7280-smmu-500 66 - qcom,sc7280-smmu-500
74 - qcom,sc8180x-smmu-500 67 - qcom,sc8180x-smmu-500
75 - qcom,sc8280xp-smmu-500 68 - qcom,sc8280xp-smmu-500
76 - qcom,sdm845-smmu-500 69 - qcom,sdm845-smmu-500
77 - qcom,sm6115-smmu-500 70 - qcom,sm6115-smmu-500
78 - qcom,sm6350-smmu-500 71 - qcom,sm6350-smmu-500
79 - qcom,sm6375-smmu-500 72 - qcom,sm6375-smmu-500
80 - qcom,sm8150-smmu-500 73 - qcom,sm8150-smmu-500
81 - qcom,sm8250-smmu-500 74 - qcom,sm8250-smmu-500
82 - qcom,sm8350-smmu-500 75 - qcom,sm8350-smmu-500
83 - qcom,sm8450-smmu-500 76 - qcom,sm8450-smmu-500
84 - const: arm,mmu-500 77 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implemen !! 78
86 items: !! 79 - description: Qcom Adreno GPUs implementing "arm,smmu-500"
87 - enum: <<
88 - qcom,qcm2290-smmu-500 <<
89 - qcom,sa8255p-smmu-500 <<
90 - qcom,sa8775p-smmu-500 <<
91 - qcom,sc7280-smmu-500 <<
92 - qcom,sc8180x-smmu-500 <<
93 - qcom,sc8280xp-smmu-500 <<
94 - qcom,sm6115-smmu-500 <<
95 - qcom,sm6125-smmu-500 <<
96 - qcom,sm8150-smmu-500 <<
97 - qcom,sm8250-smmu-500 <<
98 - qcom,sm8350-smmu-500 <<
99 - qcom,sm8450-smmu-500 <<
100 - qcom,sm8550-smmu-500 <<
101 - qcom,sm8650-smmu-500 <<
102 - qcom,x1e80100-smmu-500 <<
103 - const: qcom,adreno-smmu <<
104 - const: qcom,smmu-500 <<
105 - const: arm,mmu-500 <<
106 - description: Qcom Adreno GPUs implemen <<
107 deprecated: true <<
108 items: 80 items:
109 # Do not add additional SoC to this <<
110 - enum: 81 - enum:
111 - qcom,sc7280-smmu-500 82 - qcom,sc7280-smmu-500
112 - qcom,sm8150-smmu-500 83 - qcom,sm8150-smmu-500
113 - qcom,sm8250-smmu-500 84 - qcom,sm8250-smmu-500
114 - const: qcom,adreno-smmu 85 - const: qcom,adreno-smmu
115 - const: arm,mmu-500 86 - const: arm,mmu-500
116 - description: Qcom Adreno GPUs implemen 87 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
117 items: 88 items:
118 - enum: 89 - enum:
119 - qcom,msm8996-smmu-v2 90 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2 91 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2 92 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2 93 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2 94 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2 <<
125 - const: qcom,adreno-smmu 95 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2 96 - const: qcom,smmu-v2
127 - description: Qcom Adreno GPUs on Googl 97 - description: Qcom Adreno GPUs on Google Cheza platform
128 items: 98 items:
129 - const: qcom,sdm845-smmu-v2 99 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2 100 - const: qcom,smmu-v2
131 - description: Marvell SoCs implementing 101 - description: Marvell SoCs implementing "arm,mmu-500"
132 items: 102 items:
133 - const: marvell,ap806-smmu-500 103 - const: marvell,ap806-smmu-500
134 - const: arm,mmu-500 104 - const: arm,mmu-500
135 - description: NVIDIA SoCs that require 105 - description: NVIDIA SoCs that require memory controller interaction
136 and may program multiple ARM MMU-500 106 and may program multiple ARM MMU-500s identically with the memory
137 controller interleaving translations 107 controller interleaving translations between multiple instances
138 for improved performance. 108 for improved performance.
139 items: 109 items:
140 - enum: 110 - enum:
141 - nvidia,tegra186-smmu 111 - nvidia,tegra186-smmu
142 - nvidia,tegra194-smmu 112 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu 113 - nvidia,tegra234-smmu
144 - const: nvidia,smmu-500 114 - const: nvidia,smmu-500
145 - items: 115 - items:
146 - const: arm,mmu-500 116 - const: arm,mmu-500
147 - const: arm,smmu-v2 117 - const: arm,smmu-v2
148 - items: 118 - items:
149 - enum: 119 - enum:
150 - arm,mmu-400 120 - arm,mmu-400
151 - arm,mmu-401 121 - arm,mmu-401
152 - const: arm,smmu-v1 122 - const: arm,smmu-v1
153 - enum: 123 - enum:
154 - arm,smmu-v1 124 - arm,smmu-v1
155 - arm,smmu-v2 125 - arm,smmu-v2
156 - arm,mmu-400 126 - arm,mmu-400
157 - arm,mmu-401 127 - arm,mmu-401
158 - arm,mmu-500 128 - arm,mmu-500
159 - cavium,smmu-v2 129 - cavium,smmu-v2
160 130
161 reg: 131 reg:
162 minItems: 1 132 minItems: 1
163 maxItems: 2 133 maxItems: 2
164 134
165 '#global-interrupts': 135 '#global-interrupts':
166 description: The number of global interrup 136 description: The number of global interrupts exposed by the device.
167 $ref: /schemas/types.yaml#/definitions/uin 137 $ref: /schemas/types.yaml#/definitions/uint32
168 minimum: 0 138 minimum: 0
169 maximum: 260 # 2 secure, 2 non-secure, a 139 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
170 140
171 '#iommu-cells': 141 '#iommu-cells':
172 enum: [ 1, 2 ] 142 enum: [ 1, 2 ]
173 description: | 143 description: |
174 See Documentation/devicetree/bindings/io 144 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
175 value of 1, each IOMMU specifier represe 145 value of 1, each IOMMU specifier represents a distinct stream ID emitted
176 by that device into the relevant SMMU. 146 by that device into the relevant SMMU.
177 147
178 SMMUs with stream matching support and c 148 SMMUs with stream matching support and complex masters may use a value of
179 2, where the second cell of the IOMMU sp 149 2, where the second cell of the IOMMU specifier represents an SMR mask to
180 combine with the ID in the first cell. 150 combine with the ID in the first cell. Care must be taken to ensure the
181 set of matched IDs does not result in co 151 set of matched IDs does not result in conflicts.
182 152
183 interrupts: 153 interrupts:
184 minItems: 1 154 minItems: 1
185 maxItems: 388 # 260 plus 128 contexts 155 maxItems: 388 # 260 plus 128 contexts
186 description: | 156 description: |
187 Interrupt list, with the first #global-i 157 Interrupt list, with the first #global-interrupts entries corresponding to
188 the global interrupts and any following 158 the global interrupts and any following entries corresponding to context
189 interrupts, specified in order of their 159 interrupts, specified in order of their indexing by the SMMU.
190 160
191 For SMMUv2 implementations, there must b 161 For SMMUv2 implementations, there must be exactly one interrupt per
192 context bank. In the case of a single, c 162 context bank. In the case of a single, combined interrupt, it must be
193 listed multiple times. 163 listed multiple times.
194 164
195 dma-coherent: 165 dma-coherent:
196 description: | 166 description: |
197 Present if page table walks made by the 167 Present if page table walks made by the SMMU are cache coherent with the
198 CPU. 168 CPU.
199 169
200 NOTE: this only applies to the SMMU itse 170 NOTE: this only applies to the SMMU itself, not masters connected
201 upstream of the SMMU. 171 upstream of the SMMU.
202 172
203 calxeda,smmu-secure-config-access: 173 calxeda,smmu-secure-config-access:
204 type: boolean 174 type: boolean
205 description: 175 description:
206 Enable proper handling of buggy implemen 176 Enable proper handling of buggy implementations that always use secure
207 access to SMMU configuration registers. 177 access to SMMU configuration registers. In this case non-secure aliases of
208 secure registers have to be used during 178 secure registers have to be used during SMMU configuration.
209 179
210 stream-match-mask: 180 stream-match-mask:
211 $ref: /schemas/types.yaml#/definitions/uin 181 $ref: /schemas/types.yaml#/definitions/uint32
212 description: | 182 description: |
213 For SMMUs supporting stream matching and 183 For SMMUs supporting stream matching and using #iommu-cells = <1>,
214 specifies a mask of bits to ignore when 184 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
215 be programmed into the SMRn.MASK field o 185 be programmed into the SMRn.MASK field of every stream match register
216 used). For cases where it is desirable t 186 used). For cases where it is desirable to ignore some portion of every
217 Stream ID (e.g. for certain MMU-500 conf 187 Stream ID (e.g. for certain MMU-500 configurations given globally unique
218 input IDs). This property is not valid f 188 input IDs). This property is not valid for SMMUs using stream indexing, or
219 using stream matching with #iommu-cells 189 using stream matching with #iommu-cells = <2>, and may be ignored if
220 present in such cases. 190 present in such cases.
221 191
222 clock-names: 192 clock-names:
223 minItems: 1 193 minItems: 1
224 maxItems: 7 194 maxItems: 7
225 195
226 clocks: 196 clocks:
227 minItems: 1 197 minItems: 1
228 maxItems: 7 198 maxItems: 7
229 199
230 power-domains: 200 power-domains:
231 minItems: 1 201 minItems: 1
232 maxItems: 3 202 maxItems: 3
233 203
234 nvidia,memory-controller: 204 nvidia,memory-controller:
235 description: | 205 description: |
236 A phandle to the memory controller on NV 206 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
237 The memory controller needs to be progra 207 The memory controller needs to be programmed with a mapping of memory
238 client IDs to ARM SMMU stream IDs. 208 client IDs to ARM SMMU stream IDs.
239 209
240 If this property is absent, the mapping 210 If this property is absent, the mapping programmed by early firmware
241 will be used and it is not guaranteed th 211 will be used and it is not guaranteed that IOMMU translations will be
242 enabled for any given device. 212 enabled for any given device.
243 $ref: /schemas/types.yaml#/definitions/pha 213 $ref: /schemas/types.yaml#/definitions/phandle
244 214
245 required: 215 required:
246 - compatible 216 - compatible
247 - reg 217 - reg
248 - '#global-interrupts' 218 - '#global-interrupts'
249 - '#iommu-cells' 219 - '#iommu-cells'
250 - interrupts 220 - interrupts
251 221
252 additionalProperties: false 222 additionalProperties: false
253 223
254 allOf: 224 allOf:
255 - if: 225 - if:
256 properties: 226 properties:
257 compatible: 227 compatible:
258 contains: 228 contains:
259 enum: 229 enum:
260 - nvidia,tegra186-smmu 230 - nvidia,tegra186-smmu
261 - nvidia,tegra194-smmu 231 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu 232 - nvidia,tegra234-smmu
263 then: 233 then:
264 properties: 234 properties:
265 reg: 235 reg:
266 minItems: 1 236 minItems: 1
267 maxItems: 2 237 maxItems: 2
268 238
269 # The reference to the memory controller 239 # The reference to the memory controller is required to ensure that the
270 # memory client to stream ID mapping can 240 # memory client to stream ID mapping can be done synchronously with the
271 # IOMMU attachment. 241 # IOMMU attachment.
272 required: 242 required:
273 - nvidia,memory-controller 243 - nvidia,memory-controller
274 else: 244 else:
275 properties: 245 properties:
276 reg: 246 reg:
277 maxItems: 1 247 maxItems: 1
278 248
279 - if: 249 - if:
280 properties: 250 properties:
281 compatible: 251 compatible:
282 contains: 252 contains:
283 enum: 253 enum:
284 - qcom,msm8998-smmu-v2 254 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2 255 - qcom,sdm630-smmu-v2
286 then: 256 then:
287 anyOf: 257 anyOf:
288 - properties: 258 - properties:
289 clock-names: 259 clock-names:
290 items: 260 items:
291 - const: bus 261 - const: bus
292 clocks: 262 clocks:
293 items: 263 items:
294 - description: bus clock requi 264 - description: bus clock required for downstream bus access and for
295 the smmu ptw 265 the smmu ptw
296 - properties: 266 - properties:
297 clock-names: 267 clock-names:
298 items: 268 items:
299 - const: iface 269 - const: iface
300 - const: mem 270 - const: mem
301 - const: mem_iface 271 - const: mem_iface
302 clocks: 272 clocks:
303 items: 273 items:
304 - description: interface clock 274 - description: interface clock required to access smmu's registers
305 through the TCU's programm 275 through the TCU's programming interface.
306 - description: bus clock requi 276 - description: bus clock required for memory access
307 - description: bus clock requi 277 - description: bus clock required for GPU memory access
308 - properties: 278 - properties:
309 clock-names: 279 clock-names:
310 items: 280 items:
311 - const: iface-mm 281 - const: iface-mm
312 - const: iface-smmu 282 - const: iface-smmu
313 - const: bus-smmu <<
314 clocks: <<
315 items: <<
316 - description: interface clock <<
317 through the TCU's programm <<
318 - description: interface clock <<
319 through the TCU's programm <<
320 - description: bus clock requi <<
321 <<
322 - if: <<
323 properties: <<
324 compatible: <<
325 contains: <<
326 enum: <<
327 - qcom,sm6375-smmu-v2 <<
328 then: <<
329 anyOf: <<
330 - properties: <<
331 clock-names: <<
332 items: <<
333 - const: bus <<
334 clocks: <<
335 items: <<
336 - description: bus clock requi <<
337 the smmu ptw <<
338 - properties: <<
339 clock-names: <<
340 items: <<
341 - const: iface <<
342 - const: mem <<
343 - const: mem_iface <<
344 clocks: <<
345 items: <<
346 - description: interface clock <<
347 through the TCU's programm <<
348 - description: bus clock requi <<
349 - description: bus clock requi <<
350 - properties: <<
351 clock-names: <<
352 items: <<
353 - const: iface-mm <<
354 - const: iface-smmu <<
355 - const: bus-mm 283 - const: bus-mm
356 - const: bus-smmu 284 - const: bus-smmu
357 clocks: 285 clocks:
358 items: 286 items:
359 - description: interface clock 287 - description: interface clock required to access mnoc's registers
360 through the TCU's programm 288 through the TCU's programming interface.
361 - description: interface clock 289 - description: interface clock required to access smmu's registers
362 through the TCU's programm 290 through the TCU's programming interface.
363 - description: bus clock requi 291 - description: bus clock required for downstream bus access
364 - description: bus clock requi 292 - description: bus clock required for the smmu ptw
365 293
366 - if: 294 - if:
367 properties: 295 properties:
368 compatible: 296 compatible:
369 contains: 297 contains:
370 enum: 298 enum:
371 - qcom,msm8996-smmu-v2 299 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2 300 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2 301 - qcom,sdm845-smmu-v2
374 then: 302 then:
375 properties: 303 properties:
376 clock-names: 304 clock-names:
377 items: 305 items:
378 - const: bus 306 - const: bus
379 - const: iface 307 - const: iface
380 308
381 clocks: 309 clocks:
382 items: 310 items:
383 - description: bus clock required 311 - description: bus clock required for downstream bus access and for
384 the smmu ptw 312 the smmu ptw
385 - description: interface clock req 313 - description: interface clock required to access smmu's registers
386 through the TCU's programming 314 through the TCU's programming interface.
387 315
388 - if: 316 - if:
389 properties: 317 properties:
390 compatible: 318 compatible:
391 contains: 319 contains:
392 enum: !! 320 const: qcom,sc7280-smmu-500
393 - qcom,sa8775p-smmu-500 <<
394 - qcom,sc7280-smmu-500 <<
395 - qcom,sc8280xp-smmu-500 <<
396 then: 321 then:
397 properties: 322 properties:
398 clock-names: 323 clock-names:
399 items: 324 items:
400 - const: gcc_gpu_memnoc_gfx_clk 325 - const: gcc_gpu_memnoc_gfx_clk
401 - const: gcc_gpu_snoc_dvm_gfx_clk 326 - const: gcc_gpu_snoc_dvm_gfx_clk
402 - const: gpu_cc_ahb_clk 327 - const: gpu_cc_ahb_clk
403 - const: gpu_cc_hlos1_vote_gpu_smm 328 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
404 - const: gpu_cc_cx_gmu_clk 329 - const: gpu_cc_cx_gmu_clk
405 - const: gpu_cc_hub_cx_int_clk 330 - const: gpu_cc_hub_cx_int_clk
406 - const: gpu_cc_hub_aon_clk 331 - const: gpu_cc_hub_aon_clk
407 332
408 clocks: 333 clocks:
409 items: 334 items:
410 - description: GPU memnoc_gfx cloc 335 - description: GPU memnoc_gfx clock
411 - description: GPU snoc_dvm_gfx cl 336 - description: GPU snoc_dvm_gfx clock
412 - description: GPU ahb clock 337 - description: GPU ahb clock
413 - description: GPU hlos1_vote_GPU 338 - description: GPU hlos1_vote_GPU smmu clock
414 - description: GPU cx_gmu clock 339 - description: GPU cx_gmu clock
415 - description: GPU hub_cx_int cloc 340 - description: GPU hub_cx_int clock
416 - description: GPU hub_aon clock 341 - description: GPU hub_aon clock
417 342
418 - if: 343 - if:
419 properties: 344 properties:
420 compatible: 345 compatible:
421 contains: 346 contains:
422 enum: 347 enum:
423 - qcom,sc8180x-smmu-500 <<
424 - qcom,sm6350-smmu-v2 348 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2 <<
426 - qcom,sm8150-smmu-500 349 - qcom,sm8150-smmu-500
427 - qcom,sm8250-smmu-500 350 - qcom,sm8250-smmu-500
428 then: 351 then:
429 properties: 352 properties:
430 clock-names: 353 clock-names:
431 items: 354 items:
432 - const: ahb 355 - const: ahb
433 - const: bus 356 - const: bus
434 - const: iface 357 - const: iface
435 358
436 clocks: 359 clocks:
437 items: 360 items:
438 - description: bus clock required 361 - description: bus clock required for AHB bus access
439 - description: bus clock required 362 - description: bus clock required for downstream bus access and for
440 the smmu ptw 363 the smmu ptw
441 - description: interface clock req 364 - description: interface clock required to access smmu's registers
442 through the TCU's programming 365 through the TCU's programming interface.
443 366
444 - if: <<
445 properties: <<
446 compatible: <<
447 items: <<
448 - enum: <<
449 - qcom,sm8350-smmu-500 <<
450 - const: qcom,adreno-smmu <<
451 - const: qcom,smmu-500 <<
452 - const: arm,mmu-500 <<
453 then: <<
454 properties: <<
455 clock-names: <<
456 items: <<
457 - const: bus <<
458 - const: iface <<
459 - const: ahb <<
460 - const: hlos1_vote_gpu_smmu <<
461 - const: cx_gmu <<
462 - const: hub_cx_int <<
463 - const: hub_aon <<
464 clocks: <<
465 minItems: 7 <<
466 maxItems: 7 <<
467 <<
468 - if: <<
469 properties: <<
470 compatible: <<
471 items: <<
472 - enum: <<
473 - qcom,qcm2290-smmu-500 <<
474 - qcom,sm6115-smmu-500 <<
475 - qcom,sm6125-smmu-500 <<
476 - const: qcom,adreno-smmu <<
477 - const: qcom,smmu-500 <<
478 - const: arm,mmu-500 <<
479 then: <<
480 properties: <<
481 clock-names: <<
482 items: <<
483 - const: mem <<
484 - const: hlos <<
485 - const: iface <<
486 <<
487 clocks: <<
488 items: <<
489 - description: GPU memory bus cloc <<
490 - description: Voter clock require <<
491 - description: Interface clock req <<
492 <<
493 - if: <<
494 properties: <<
495 compatible: <<
496 items: <<
497 - const: qcom,sm8450-smmu-500 <<
498 - const: qcom,adreno-smmu <<
499 - const: qcom,smmu-500 <<
500 - const: arm,mmu-500 <<
501 <<
502 then: <<
503 properties: <<
504 clock-names: <<
505 items: <<
506 - const: gmu <<
507 - const: hub <<
508 - const: hlos <<
509 - const: bus <<
510 - const: iface <<
511 - const: ahb <<
512 <<
513 clocks: <<
514 items: <<
515 - description: GMU clock <<
516 - description: GPU HUB clock <<
517 - description: HLOS vote clock <<
518 - description: GPU memory bus cloc <<
519 - description: GPU SNoC bus clock <<
520 - description: GPU AHB clock <<
521 <<
522 - if: <<
523 properties: <<
524 compatible: <<
525 items: <<
526 - enum: <<
527 - qcom,sm8550-smmu-500 <<
528 - qcom,sm8650-smmu-500 <<
529 - qcom,x1e80100-smmu-500 <<
530 - const: qcom,adreno-smmu <<
531 - const: qcom,smmu-500 <<
532 - const: arm,mmu-500 <<
533 then: <<
534 properties: <<
535 clock-names: <<
536 items: <<
537 - const: hlos <<
538 - const: bus <<
539 - const: iface <<
540 - const: ahb <<
541 <<
542 clocks: <<
543 items: <<
544 - description: HLOS vote clock <<
545 - description: GPU memory bus cloc <<
546 - description: GPU SNoC bus clock <<
547 - description: GPU AHB clock <<
548 <<
549 # Disallow clocks for all other platforms wi 367 # Disallow clocks for all other platforms with specific compatibles
550 - if: 368 - if:
551 properties: 369 properties:
552 compatible: 370 compatible:
553 contains: 371 contains:
554 enum: 372 enum:
555 - cavium,smmu-v2 373 - cavium,smmu-v2
556 - marvell,ap806-smmu-500 374 - marvell,ap806-smmu-500
557 - nvidia,smmu-500 375 - nvidia,smmu-500
558 - qcom,qcs8300-smmu-500 !! 376 - qcom,qcm2290-smmu-500
559 - qcom,qdu1000-smmu-500 377 - qcom,qdu1000-smmu-500
560 - qcom,sa8255p-smmu-500 !! 378 - qcom,sa8775p-smmu-500
561 - qcom,sc7180-smmu-500 379 - qcom,sc7180-smmu-500
>> 380 - qcom,sc8180x-smmu-500
>> 381 - qcom,sc8280xp-smmu-500
562 - qcom,sdm670-smmu-500 382 - qcom,sdm670-smmu-500
563 - qcom,sdm845-smmu-500 383 - qcom,sdm845-smmu-500
564 - qcom,sdx55-smmu-500 384 - qcom,sdx55-smmu-500
565 - qcom,sdx65-smmu-500 385 - qcom,sdx65-smmu-500
>> 386 - qcom,sm6115-smmu-500
>> 387 - qcom,sm6125-smmu-500
566 - qcom,sm6350-smmu-500 388 - qcom,sm6350-smmu-500
567 - qcom,sm6375-smmu-500 389 - qcom,sm6375-smmu-500
>> 390 - qcom,sm8350-smmu-500
>> 391 - qcom,sm8450-smmu-500
568 then: 392 then:
569 properties: 393 properties:
570 clock-names: false 394 clock-names: false
571 clocks: false 395 clocks: false
572 396
573 - if: 397 - if:
574 properties: 398 properties:
575 compatible: 399 compatible:
576 contains: 400 contains:
577 const: qcom,sm6375-smmu-500 401 const: qcom,sm6375-smmu-500
578 then: 402 then:
579 properties: 403 properties:
580 power-domains: 404 power-domains:
581 items: 405 items:
582 - description: SNoC MMU TBU RT GDS 406 - description: SNoC MMU TBU RT GDSC
583 - description: SNoC MMU TBU NRT GD 407 - description: SNoC MMU TBU NRT GDSC
584 - description: SNoC TURING MMU TBU 408 - description: SNoC TURING MMU TBU0 GDSC
585 409
586 required: 410 required:
587 - power-domains 411 - power-domains
588 else: 412 else:
589 properties: 413 properties:
590 power-domains: 414 power-domains:
591 maxItems: 1 415 maxItems: 1
592 416
593 examples: 417 examples:
594 - |+ 418 - |+
595 /* SMMU with stream matching or stream ind 419 /* SMMU with stream matching or stream indexing */
596 smmu1: iommu@ba5e0000 { 420 smmu1: iommu@ba5e0000 {
597 compatible = "arm,smmu-v1"; 421 compatible = "arm,smmu-v1";
598 reg = <0xba5e0000 0x10000>; 422 reg = <0xba5e0000 0x10000>;
599 #global-interrupts = <2>; 423 #global-interrupts = <2>;
600 interrupts = <0 32 4>, 424 interrupts = <0 32 4>,
601 <0 33 4>, 425 <0 33 4>,
602 <0 34 4>, /* This is 426 <0 34 4>, /* This is the first context interrupt */
603 <0 35 4>, 427 <0 35 4>,
604 <0 36 4>, 428 <0 36 4>,
605 <0 37 4>; 429 <0 37 4>;
606 #iommu-cells = <1>; 430 #iommu-cells = <1>;
607 }; 431 };
608 432
609 /* device with two stream IDs, 0 and 7 */ 433 /* device with two stream IDs, 0 and 7 */
610 master1 { 434 master1 {
611 iommus = <&smmu1 0>, 435 iommus = <&smmu1 0>,
612 <&smmu1 7>; 436 <&smmu1 7>;
613 }; 437 };
614 438
615 439
616 /* SMMU with stream matching */ 440 /* SMMU with stream matching */
617 smmu2: iommu@ba5f0000 { 441 smmu2: iommu@ba5f0000 {
618 compatible = "arm,smmu-v1"; 442 compatible = "arm,smmu-v1";
619 reg = <0xba5f0000 0x10000>; 443 reg = <0xba5f0000 0x10000>;
620 #global-interrupts = <2>; 444 #global-interrupts = <2>;
621 interrupts = <0 38 4>, 445 interrupts = <0 38 4>,
622 <0 39 4>, 446 <0 39 4>,
623 <0 40 4>, /* This is 447 <0 40 4>, /* This is the first context interrupt */
624 <0 41 4>, 448 <0 41 4>,
625 <0 42 4>, 449 <0 42 4>,
626 <0 43 4>; 450 <0 43 4>;
627 #iommu-cells = <2>; 451 #iommu-cells = <2>;
628 }; 452 };
629 453
630 /* device with stream IDs 0 and 7 */ 454 /* device with stream IDs 0 and 7 */
631 master2 { 455 master2 {
632 iommus = <&smmu2 0 0>, 456 iommus = <&smmu2 0 0>,
633 <&smmu2 7 0>; 457 <&smmu2 7 0>;
634 }; 458 };
635 459
636 /* device with stream IDs 1, 17, 33 and 49 460 /* device with stream IDs 1, 17, 33 and 49 */
637 master3 { 461 master3 {
638 iommus = <&smmu2 1 0x30>; 462 iommus = <&smmu2 1 0x30>;
639 }; 463 };
640 464
641 465
642 /* ARM MMU-500 with 10-bit stream ID input 466 /* ARM MMU-500 with 10-bit stream ID input configuration */
643 smmu3: iommu@ba600000 { 467 smmu3: iommu@ba600000 {
644 compatible = "arm,mmu-500", "arm,s 468 compatible = "arm,mmu-500", "arm,smmu-v2";
645 reg = <0xba600000 0x10000>; 469 reg = <0xba600000 0x10000>;
646 #global-interrupts = <2>; 470 #global-interrupts = <2>;
647 interrupts = <0 44 4>, 471 interrupts = <0 44 4>,
648 <0 45 4>, 472 <0 45 4>,
649 <0 46 4>, /* This is 473 <0 46 4>, /* This is the first context interrupt */
650 <0 47 4>, 474 <0 47 4>,
651 <0 48 4>, 475 <0 48 4>,
652 <0 49 4>; 476 <0 49 4>;
653 #iommu-cells = <1>; 477 #iommu-cells = <1>;
654 /* always ignore appended 5-bit TB 478 /* always ignore appended 5-bit TBU number */
655 stream-match-mask = <0x7c00>; 479 stream-match-mask = <0x7c00>;
656 }; 480 };
657 481
658 bus { 482 bus {
659 /* bus whose child devices emit on 483 /* bus whose child devices emit one unique 10-bit stream
660 ID each, but may master through 484 ID each, but may master through multiple SMMU TBUs */
661 iommu-map = <0 &smmu3 0 0x400>; 485 iommu-map = <0 &smmu3 0 0x400>;
662 486
663 487
664 }; 488 };
665 489
666 - |+ 490 - |+
667 /* Qcom's arm,smmu-v2 implementation */ 491 /* Qcom's arm,smmu-v2 implementation */
668 #include <dt-bindings/interrupt-controller 492 #include <dt-bindings/interrupt-controller/arm-gic.h>
669 #include <dt-bindings/interrupt-controller 493 #include <dt-bindings/interrupt-controller/irq.h>
670 smmu4: iommu@d00000 { 494 smmu4: iommu@d00000 {
671 compatible = "qcom,msm8996-smmu-v2", "qc 495 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
672 reg = <0xd00000 0x10000>; 496 reg = <0xd00000 0x10000>;
673 497
674 #global-interrupts = <1>; 498 #global-interrupts = <1>;
675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_ 499 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH> 500 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH> 501 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
678 #iommu-cells = <1>; 502 #iommu-cells = <1>;
679 power-domains = <&mmcc 0>; 503 power-domains = <&mmcc 0>;
680 504
681 clocks = <&mmcc 123>, 505 clocks = <&mmcc 123>,
682 <&mmcc 124>; 506 <&mmcc 124>;
683 clock-names = "bus", "iface"; 507 clock-names = "bus", "iface";
684 }; 508 };
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