1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,s 4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM System MMU Architecture Implementat 7 title: ARM System MMU Architecture Implementation
8 8
9 maintainers: 9 maintainers:
10 - Will Deacon <will@kernel.org> 10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com> 11 - Robin Murphy <Robin.Murphy@arm.com>
12 12
13 description: |+ 13 description: |+
14 ARM SoCs may contain an implementation of th 14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be u 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters extern 16 of address translation to bus masters external to the CPU.
17 17
18 The SMMU may also raise interrupts in respon 18 The SMMU may also raise interrupts in response to various fault
19 conditions. 19 conditions.
20 20
21 properties: 21 properties:
22 $nodename: 22 $nodename:
23 pattern: "^iommu@[0-9a-f]*" 23 pattern: "^iommu@[0-9a-f]*"
24 compatible: 24 compatible:
25 oneOf: 25 oneOf:
26 - description: Qcom SoCs implementing "a 26 - description: Qcom SoCs implementing "arm,smmu-v2"
27 items: 27 items:
28 - enum: 28 - enum:
29 - qcom,msm8996-smmu-v2 29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2 30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2 31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2 32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2 33 - const: qcom,smmu-v2
34 34
35 - description: Qcom SoCs implementing "q 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36 items: 36 items:
37 - enum: 37 - enum:
38 - qcom,qcm2290-smmu-500 38 - qcom,qcm2290-smmu-500
39 - qcom,qcs8300-smmu-500 <<
40 - qcom,qdu1000-smmu-500 39 - qcom,qdu1000-smmu-500
41 - qcom,sa8255p-smmu-500 <<
42 - qcom,sa8775p-smmu-500 40 - qcom,sa8775p-smmu-500
43 - qcom,sc7180-smmu-500 41 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500 42 - qcom,sc7280-smmu-500
45 - qcom,sc8180x-smmu-500 43 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500 44 - qcom,sc8280xp-smmu-500
47 - qcom,sdm670-smmu-500 45 - qcom,sdm670-smmu-500
48 - qcom,sdm845-smmu-500 46 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500 47 - qcom,sdx55-smmu-500
50 - qcom,sdx65-smmu-500 48 - qcom,sdx65-smmu-500
51 - qcom,sdx75-smmu-500 49 - qcom,sdx75-smmu-500
52 - qcom,sm6115-smmu-500 50 - qcom,sm6115-smmu-500
53 - qcom,sm6125-smmu-500 51 - qcom,sm6125-smmu-500
54 - qcom,sm6350-smmu-500 52 - qcom,sm6350-smmu-500
55 - qcom,sm6375-smmu-500 53 - qcom,sm6375-smmu-500
56 - qcom,sm8150-smmu-500 54 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500 55 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500 56 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500 57 - qcom,sm8450-smmu-500
60 - qcom,sm8550-smmu-500 58 - qcom,sm8550-smmu-500
61 - qcom,sm8650-smmu-500 <<
62 - qcom,x1e80100-smmu-500 <<
63 - const: qcom,smmu-500 59 - const: qcom,smmu-500
64 - const: arm,mmu-500 60 - const: arm,mmu-500
65 61
66 - description: Qcom SoCs implementing "a 62 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
67 deprecated: true 63 deprecated: true
68 items: 64 items:
69 # Do not add additional SoC to this 65 # Do not add additional SoC to this list. Instead use two previous lists.
70 - enum: 66 - enum:
71 - qcom,qcm2290-smmu-500 67 - qcom,qcm2290-smmu-500
72 - qcom,sc7180-smmu-500 68 - qcom,sc7180-smmu-500
73 - qcom,sc7280-smmu-500 69 - qcom,sc7280-smmu-500
74 - qcom,sc8180x-smmu-500 70 - qcom,sc8180x-smmu-500
75 - qcom,sc8280xp-smmu-500 71 - qcom,sc8280xp-smmu-500
76 - qcom,sdm845-smmu-500 72 - qcom,sdm845-smmu-500
77 - qcom,sm6115-smmu-500 73 - qcom,sm6115-smmu-500
78 - qcom,sm6350-smmu-500 74 - qcom,sm6350-smmu-500
79 - qcom,sm6375-smmu-500 75 - qcom,sm6375-smmu-500
80 - qcom,sm8150-smmu-500 76 - qcom,sm8150-smmu-500
81 - qcom,sm8250-smmu-500 77 - qcom,sm8250-smmu-500
82 - qcom,sm8350-smmu-500 78 - qcom,sm8350-smmu-500
83 - qcom,sm8450-smmu-500 79 - qcom,sm8450-smmu-500
84 - const: arm,mmu-500 80 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implemen 81 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
86 items: 82 items:
87 - enum: 83 - enum:
88 - qcom,qcm2290-smmu-500 <<
89 - qcom,sa8255p-smmu-500 <<
90 - qcom,sa8775p-smmu-500 84 - qcom,sa8775p-smmu-500
91 - qcom,sc7280-smmu-500 85 - qcom,sc7280-smmu-500
92 - qcom,sc8180x-smmu-500 <<
93 - qcom,sc8280xp-smmu-500 86 - qcom,sc8280xp-smmu-500
94 - qcom,sm6115-smmu-500 87 - qcom,sm6115-smmu-500
95 - qcom,sm6125-smmu-500 88 - qcom,sm6125-smmu-500
96 - qcom,sm8150-smmu-500 89 - qcom,sm8150-smmu-500
97 - qcom,sm8250-smmu-500 90 - qcom,sm8250-smmu-500
98 - qcom,sm8350-smmu-500 91 - qcom,sm8350-smmu-500
99 - qcom,sm8450-smmu-500 <<
100 - qcom,sm8550-smmu-500 <<
101 - qcom,sm8650-smmu-500 <<
102 - qcom,x1e80100-smmu-500 <<
103 - const: qcom,adreno-smmu 92 - const: qcom,adreno-smmu
104 - const: qcom,smmu-500 93 - const: qcom,smmu-500
105 - const: arm,mmu-500 94 - const: arm,mmu-500
106 - description: Qcom Adreno GPUs implemen 95 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
107 deprecated: true 96 deprecated: true
108 items: 97 items:
109 # Do not add additional SoC to this 98 # Do not add additional SoC to this list. Instead use previous list.
110 - enum: 99 - enum:
111 - qcom,sc7280-smmu-500 100 - qcom,sc7280-smmu-500
112 - qcom,sm8150-smmu-500 101 - qcom,sm8150-smmu-500
113 - qcom,sm8250-smmu-500 102 - qcom,sm8250-smmu-500
114 - const: qcom,adreno-smmu 103 - const: qcom,adreno-smmu
115 - const: arm,mmu-500 104 - const: arm,mmu-500
116 - description: Qcom Adreno GPUs implemen 105 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
117 items: 106 items:
118 - enum: 107 - enum:
119 - qcom,msm8996-smmu-v2 108 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2 109 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2 110 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2 111 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2 112 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2 <<
125 - const: qcom,adreno-smmu 113 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2 114 - const: qcom,smmu-v2
127 - description: Qcom Adreno GPUs on Googl 115 - description: Qcom Adreno GPUs on Google Cheza platform
128 items: 116 items:
129 - const: qcom,sdm845-smmu-v2 117 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2 118 - const: qcom,smmu-v2
131 - description: Marvell SoCs implementing 119 - description: Marvell SoCs implementing "arm,mmu-500"
132 items: 120 items:
133 - const: marvell,ap806-smmu-500 121 - const: marvell,ap806-smmu-500
134 - const: arm,mmu-500 122 - const: arm,mmu-500
135 - description: NVIDIA SoCs that require 123 - description: NVIDIA SoCs that require memory controller interaction
136 and may program multiple ARM MMU-500 124 and may program multiple ARM MMU-500s identically with the memory
137 controller interleaving translations 125 controller interleaving translations between multiple instances
138 for improved performance. 126 for improved performance.
139 items: 127 items:
140 - enum: 128 - enum:
141 - nvidia,tegra186-smmu 129 - nvidia,tegra186-smmu
142 - nvidia,tegra194-smmu 130 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu 131 - nvidia,tegra234-smmu
144 - const: nvidia,smmu-500 132 - const: nvidia,smmu-500
145 - items: 133 - items:
146 - const: arm,mmu-500 134 - const: arm,mmu-500
147 - const: arm,smmu-v2 135 - const: arm,smmu-v2
148 - items: 136 - items:
149 - enum: 137 - enum:
150 - arm,mmu-400 138 - arm,mmu-400
151 - arm,mmu-401 139 - arm,mmu-401
152 - const: arm,smmu-v1 140 - const: arm,smmu-v1
153 - enum: 141 - enum:
154 - arm,smmu-v1 142 - arm,smmu-v1
155 - arm,smmu-v2 143 - arm,smmu-v2
156 - arm,mmu-400 144 - arm,mmu-400
157 - arm,mmu-401 145 - arm,mmu-401
158 - arm,mmu-500 146 - arm,mmu-500
159 - cavium,smmu-v2 147 - cavium,smmu-v2
160 148
161 reg: 149 reg:
162 minItems: 1 150 minItems: 1
163 maxItems: 2 151 maxItems: 2
164 152
165 '#global-interrupts': 153 '#global-interrupts':
166 description: The number of global interrup 154 description: The number of global interrupts exposed by the device.
167 $ref: /schemas/types.yaml#/definitions/uin 155 $ref: /schemas/types.yaml#/definitions/uint32
168 minimum: 0 156 minimum: 0
169 maximum: 260 # 2 secure, 2 non-secure, a 157 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
170 158
171 '#iommu-cells': 159 '#iommu-cells':
172 enum: [ 1, 2 ] 160 enum: [ 1, 2 ]
173 description: | 161 description: |
174 See Documentation/devicetree/bindings/io 162 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
175 value of 1, each IOMMU specifier represe 163 value of 1, each IOMMU specifier represents a distinct stream ID emitted
176 by that device into the relevant SMMU. 164 by that device into the relevant SMMU.
177 165
178 SMMUs with stream matching support and c 166 SMMUs with stream matching support and complex masters may use a value of
179 2, where the second cell of the IOMMU sp 167 2, where the second cell of the IOMMU specifier represents an SMR mask to
180 combine with the ID in the first cell. 168 combine with the ID in the first cell. Care must be taken to ensure the
181 set of matched IDs does not result in co 169 set of matched IDs does not result in conflicts.
182 170
183 interrupts: 171 interrupts:
184 minItems: 1 172 minItems: 1
185 maxItems: 388 # 260 plus 128 contexts 173 maxItems: 388 # 260 plus 128 contexts
186 description: | 174 description: |
187 Interrupt list, with the first #global-i 175 Interrupt list, with the first #global-interrupts entries corresponding to
188 the global interrupts and any following 176 the global interrupts and any following entries corresponding to context
189 interrupts, specified in order of their 177 interrupts, specified in order of their indexing by the SMMU.
190 178
191 For SMMUv2 implementations, there must b 179 For SMMUv2 implementations, there must be exactly one interrupt per
192 context bank. In the case of a single, c 180 context bank. In the case of a single, combined interrupt, it must be
193 listed multiple times. 181 listed multiple times.
194 182
195 dma-coherent: 183 dma-coherent:
196 description: | 184 description: |
197 Present if page table walks made by the 185 Present if page table walks made by the SMMU are cache coherent with the
198 CPU. 186 CPU.
199 187
200 NOTE: this only applies to the SMMU itse 188 NOTE: this only applies to the SMMU itself, not masters connected
201 upstream of the SMMU. 189 upstream of the SMMU.
202 190
203 calxeda,smmu-secure-config-access: 191 calxeda,smmu-secure-config-access:
204 type: boolean 192 type: boolean
205 description: 193 description:
206 Enable proper handling of buggy implemen 194 Enable proper handling of buggy implementations that always use secure
207 access to SMMU configuration registers. 195 access to SMMU configuration registers. In this case non-secure aliases of
208 secure registers have to be used during 196 secure registers have to be used during SMMU configuration.
209 197
210 stream-match-mask: 198 stream-match-mask:
211 $ref: /schemas/types.yaml#/definitions/uin 199 $ref: /schemas/types.yaml#/definitions/uint32
212 description: | 200 description: |
213 For SMMUs supporting stream matching and 201 For SMMUs supporting stream matching and using #iommu-cells = <1>,
214 specifies a mask of bits to ignore when 202 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
215 be programmed into the SMRn.MASK field o 203 be programmed into the SMRn.MASK field of every stream match register
216 used). For cases where it is desirable t 204 used). For cases where it is desirable to ignore some portion of every
217 Stream ID (e.g. for certain MMU-500 conf 205 Stream ID (e.g. for certain MMU-500 configurations given globally unique
218 input IDs). This property is not valid f 206 input IDs). This property is not valid for SMMUs using stream indexing, or
219 using stream matching with #iommu-cells 207 using stream matching with #iommu-cells = <2>, and may be ignored if
220 present in such cases. 208 present in such cases.
221 209
222 clock-names: 210 clock-names:
223 minItems: 1 211 minItems: 1
224 maxItems: 7 212 maxItems: 7
225 213
226 clocks: 214 clocks:
227 minItems: 1 215 minItems: 1
228 maxItems: 7 216 maxItems: 7
229 217
230 power-domains: 218 power-domains:
231 minItems: 1 219 minItems: 1
232 maxItems: 3 220 maxItems: 3
233 221
234 nvidia,memory-controller: 222 nvidia,memory-controller:
235 description: | 223 description: |
236 A phandle to the memory controller on NV 224 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
237 The memory controller needs to be progra 225 The memory controller needs to be programmed with a mapping of memory
238 client IDs to ARM SMMU stream IDs. 226 client IDs to ARM SMMU stream IDs.
239 227
240 If this property is absent, the mapping 228 If this property is absent, the mapping programmed by early firmware
241 will be used and it is not guaranteed th 229 will be used and it is not guaranteed that IOMMU translations will be
242 enabled for any given device. 230 enabled for any given device.
243 $ref: /schemas/types.yaml#/definitions/pha 231 $ref: /schemas/types.yaml#/definitions/phandle
244 232
245 required: 233 required:
246 - compatible 234 - compatible
247 - reg 235 - reg
248 - '#global-interrupts' 236 - '#global-interrupts'
249 - '#iommu-cells' 237 - '#iommu-cells'
250 - interrupts 238 - interrupts
251 239
252 additionalProperties: false 240 additionalProperties: false
253 241
254 allOf: 242 allOf:
255 - if: 243 - if:
256 properties: 244 properties:
257 compatible: 245 compatible:
258 contains: 246 contains:
259 enum: 247 enum:
260 - nvidia,tegra186-smmu 248 - nvidia,tegra186-smmu
261 - nvidia,tegra194-smmu 249 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu 250 - nvidia,tegra234-smmu
263 then: 251 then:
264 properties: 252 properties:
265 reg: 253 reg:
266 minItems: 1 254 minItems: 1
267 maxItems: 2 255 maxItems: 2
268 256
269 # The reference to the memory controller 257 # The reference to the memory controller is required to ensure that the
270 # memory client to stream ID mapping can 258 # memory client to stream ID mapping can be done synchronously with the
271 # IOMMU attachment. 259 # IOMMU attachment.
272 required: 260 required:
273 - nvidia,memory-controller 261 - nvidia,memory-controller
274 else: 262 else:
275 properties: 263 properties:
276 reg: 264 reg:
277 maxItems: 1 265 maxItems: 1
278 266
279 - if: 267 - if:
280 properties: 268 properties:
281 compatible: 269 compatible:
282 contains: 270 contains:
283 enum: 271 enum:
284 - qcom,msm8998-smmu-v2 272 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2 273 - qcom,sdm630-smmu-v2
286 then: <<
287 anyOf: <<
288 - properties: <<
289 clock-names: <<
290 items: <<
291 - const: bus <<
292 clocks: <<
293 items: <<
294 - description: bus clock requi <<
295 the smmu ptw <<
296 - properties: <<
297 clock-names: <<
298 items: <<
299 - const: iface <<
300 - const: mem <<
301 - const: mem_iface <<
302 clocks: <<
303 items: <<
304 - description: interface clock <<
305 through the TCU's programm <<
306 - description: bus clock requi <<
307 - description: bus clock requi <<
308 - properties: <<
309 clock-names: <<
310 items: <<
311 - const: iface-mm <<
312 - const: iface-smmu <<
313 - const: bus-smmu <<
314 clocks: <<
315 items: <<
316 - description: interface clock <<
317 through the TCU's programm <<
318 - description: interface clock <<
319 through the TCU's programm <<
320 - description: bus clock requi <<
321 <<
322 - if: <<
323 properties: <<
324 compatible: <<
325 contains: <<
326 enum: <<
327 - qcom,sm6375-smmu-v2 274 - qcom,sm6375-smmu-v2
328 then: 275 then:
329 anyOf: 276 anyOf:
330 - properties: 277 - properties:
331 clock-names: 278 clock-names:
332 items: 279 items:
333 - const: bus 280 - const: bus
334 clocks: 281 clocks:
335 items: 282 items:
336 - description: bus clock requi 283 - description: bus clock required for downstream bus access and for
337 the smmu ptw 284 the smmu ptw
338 - properties: 285 - properties:
339 clock-names: 286 clock-names:
340 items: 287 items:
341 - const: iface 288 - const: iface
342 - const: mem 289 - const: mem
343 - const: mem_iface 290 - const: mem_iface
344 clocks: 291 clocks:
345 items: 292 items:
346 - description: interface clock 293 - description: interface clock required to access smmu's registers
347 through the TCU's programm 294 through the TCU's programming interface.
348 - description: bus clock requi 295 - description: bus clock required for memory access
349 - description: bus clock requi 296 - description: bus clock required for GPU memory access
350 - properties: 297 - properties:
351 clock-names: 298 clock-names:
352 items: 299 items:
353 - const: iface-mm 300 - const: iface-mm
354 - const: iface-smmu 301 - const: iface-smmu
355 - const: bus-mm 302 - const: bus-mm
356 - const: bus-smmu 303 - const: bus-smmu
357 clocks: 304 clocks:
358 items: 305 items:
359 - description: interface clock 306 - description: interface clock required to access mnoc's registers
360 through the TCU's programm 307 through the TCU's programming interface.
361 - description: interface clock 308 - description: interface clock required to access smmu's registers
362 through the TCU's programm 309 through the TCU's programming interface.
363 - description: bus clock requi 310 - description: bus clock required for downstream bus access
364 - description: bus clock requi 311 - description: bus clock required for the smmu ptw
365 312
366 - if: 313 - if:
367 properties: 314 properties:
368 compatible: 315 compatible:
369 contains: 316 contains:
370 enum: 317 enum:
371 - qcom,msm8996-smmu-v2 318 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2 319 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2 320 - qcom,sdm845-smmu-v2
374 then: 321 then:
375 properties: 322 properties:
376 clock-names: 323 clock-names:
377 items: 324 items:
378 - const: bus 325 - const: bus
379 - const: iface 326 - const: iface
380 327
381 clocks: 328 clocks:
382 items: 329 items:
383 - description: bus clock required 330 - description: bus clock required for downstream bus access and for
384 the smmu ptw 331 the smmu ptw
385 - description: interface clock req 332 - description: interface clock required to access smmu's registers
386 through the TCU's programming 333 through the TCU's programming interface.
387 334
388 - if: 335 - if:
389 properties: 336 properties:
390 compatible: 337 compatible:
391 contains: 338 contains:
392 enum: 339 enum:
393 - qcom,sa8775p-smmu-500 340 - qcom,sa8775p-smmu-500
394 - qcom,sc7280-smmu-500 341 - qcom,sc7280-smmu-500
395 - qcom,sc8280xp-smmu-500 342 - qcom,sc8280xp-smmu-500
396 then: 343 then:
397 properties: 344 properties:
398 clock-names: 345 clock-names:
399 items: 346 items:
400 - const: gcc_gpu_memnoc_gfx_clk 347 - const: gcc_gpu_memnoc_gfx_clk
401 - const: gcc_gpu_snoc_dvm_gfx_clk 348 - const: gcc_gpu_snoc_dvm_gfx_clk
402 - const: gpu_cc_ahb_clk 349 - const: gpu_cc_ahb_clk
403 - const: gpu_cc_hlos1_vote_gpu_smm 350 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
404 - const: gpu_cc_cx_gmu_clk 351 - const: gpu_cc_cx_gmu_clk
405 - const: gpu_cc_hub_cx_int_clk 352 - const: gpu_cc_hub_cx_int_clk
406 - const: gpu_cc_hub_aon_clk 353 - const: gpu_cc_hub_aon_clk
407 354
408 clocks: 355 clocks:
409 items: 356 items:
410 - description: GPU memnoc_gfx cloc 357 - description: GPU memnoc_gfx clock
411 - description: GPU snoc_dvm_gfx cl 358 - description: GPU snoc_dvm_gfx clock
412 - description: GPU ahb clock 359 - description: GPU ahb clock
413 - description: GPU hlos1_vote_GPU 360 - description: GPU hlos1_vote_GPU smmu clock
414 - description: GPU cx_gmu clock 361 - description: GPU cx_gmu clock
415 - description: GPU hub_cx_int cloc 362 - description: GPU hub_cx_int clock
416 - description: GPU hub_aon clock 363 - description: GPU hub_aon clock
417 364
418 - if: 365 - if:
419 properties: 366 properties:
420 compatible: 367 compatible:
421 contains: 368 contains:
422 enum: 369 enum:
423 - qcom,sc8180x-smmu-500 <<
424 - qcom,sm6350-smmu-v2 370 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2 <<
426 - qcom,sm8150-smmu-500 371 - qcom,sm8150-smmu-500
427 - qcom,sm8250-smmu-500 372 - qcom,sm8250-smmu-500
428 then: 373 then:
429 properties: 374 properties:
430 clock-names: 375 clock-names:
431 items: 376 items:
432 - const: ahb 377 - const: ahb
433 - const: bus 378 - const: bus
434 - const: iface 379 - const: iface
435 380
436 clocks: 381 clocks:
437 items: 382 items:
438 - description: bus clock required 383 - description: bus clock required for AHB bus access
439 - description: bus clock required 384 - description: bus clock required for downstream bus access and for
440 the smmu ptw 385 the smmu ptw
441 - description: interface clock req 386 - description: interface clock required to access smmu's registers
442 through the TCU's programming 387 through the TCU's programming interface.
443 388
444 - if: 389 - if:
445 properties: 390 properties:
446 compatible: 391 compatible:
447 items: 392 items:
448 - enum: 393 - enum:
449 - qcom,sm8350-smmu-500 <<
450 - const: qcom,adreno-smmu <<
451 - const: qcom,smmu-500 <<
452 - const: arm,mmu-500 <<
453 then: <<
454 properties: <<
455 clock-names: <<
456 items: <<
457 - const: bus <<
458 - const: iface <<
459 - const: ahb <<
460 - const: hlos1_vote_gpu_smmu <<
461 - const: cx_gmu <<
462 - const: hub_cx_int <<
463 - const: hub_aon <<
464 clocks: <<
465 minItems: 7 <<
466 maxItems: 7 <<
467 <<
468 - if: <<
469 properties: <<
470 compatible: <<
471 items: <<
472 - enum: <<
473 - qcom,qcm2290-smmu-500 <<
474 - qcom,sm6115-smmu-500 394 - qcom,sm6115-smmu-500
475 - qcom,sm6125-smmu-500 395 - qcom,sm6125-smmu-500
476 - const: qcom,adreno-smmu 396 - const: qcom,adreno-smmu
477 - const: qcom,smmu-500 397 - const: qcom,smmu-500
478 - const: arm,mmu-500 398 - const: arm,mmu-500
479 then: 399 then:
480 properties: 400 properties:
481 clock-names: 401 clock-names:
482 items: 402 items:
483 - const: mem 403 - const: mem
484 - const: hlos 404 - const: hlos
485 - const: iface 405 - const: iface
486 406
487 clocks: 407 clocks:
488 items: 408 items:
489 - description: GPU memory bus cloc 409 - description: GPU memory bus clock
490 - description: Voter clock require 410 - description: Voter clock required for HLOS SMMU access
491 - description: Interface clock req 411 - description: Interface clock required for register access
492 412
493 - if: <<
494 properties: <<
495 compatible: <<
496 items: <<
497 - const: qcom,sm8450-smmu-500 <<
498 - const: qcom,adreno-smmu <<
499 - const: qcom,smmu-500 <<
500 - const: arm,mmu-500 <<
501 <<
502 then: <<
503 properties: <<
504 clock-names: <<
505 items: <<
506 - const: gmu <<
507 - const: hub <<
508 - const: hlos <<
509 - const: bus <<
510 - const: iface <<
511 - const: ahb <<
512 <<
513 clocks: <<
514 items: <<
515 - description: GMU clock <<
516 - description: GPU HUB clock <<
517 - description: HLOS vote clock <<
518 - description: GPU memory bus cloc <<
519 - description: GPU SNoC bus clock <<
520 - description: GPU AHB clock <<
521 <<
522 - if: <<
523 properties: <<
524 compatible: <<
525 items: <<
526 - enum: <<
527 - qcom,sm8550-smmu-500 <<
528 - qcom,sm8650-smmu-500 <<
529 - qcom,x1e80100-smmu-500 <<
530 - const: qcom,adreno-smmu <<
531 - const: qcom,smmu-500 <<
532 - const: arm,mmu-500 <<
533 then: <<
534 properties: <<
535 clock-names: <<
536 items: <<
537 - const: hlos <<
538 - const: bus <<
539 - const: iface <<
540 - const: ahb <<
541 <<
542 clocks: <<
543 items: <<
544 - description: HLOS vote clock <<
545 - description: GPU memory bus cloc <<
546 - description: GPU SNoC bus clock <<
547 - description: GPU AHB clock <<
548 <<
549 # Disallow clocks for all other platforms wi 413 # Disallow clocks for all other platforms with specific compatibles
550 - if: 414 - if:
551 properties: 415 properties:
552 compatible: 416 compatible:
553 contains: 417 contains:
554 enum: 418 enum:
555 - cavium,smmu-v2 419 - cavium,smmu-v2
556 - marvell,ap806-smmu-500 420 - marvell,ap806-smmu-500
557 - nvidia,smmu-500 421 - nvidia,smmu-500
558 - qcom,qcs8300-smmu-500 !! 422 - qcom,qcm2290-smmu-500
559 - qcom,qdu1000-smmu-500 423 - qcom,qdu1000-smmu-500
560 - qcom,sa8255p-smmu-500 <<
561 - qcom,sc7180-smmu-500 424 - qcom,sc7180-smmu-500
>> 425 - qcom,sc8180x-smmu-500
562 - qcom,sdm670-smmu-500 426 - qcom,sdm670-smmu-500
563 - qcom,sdm845-smmu-500 427 - qcom,sdm845-smmu-500
564 - qcom,sdx55-smmu-500 428 - qcom,sdx55-smmu-500
565 - qcom,sdx65-smmu-500 429 - qcom,sdx65-smmu-500
566 - qcom,sm6350-smmu-500 430 - qcom,sm6350-smmu-500
567 - qcom,sm6375-smmu-500 431 - qcom,sm6375-smmu-500
>> 432 - qcom,sm8350-smmu-500
>> 433 - qcom,sm8450-smmu-500
>> 434 - qcom,sm8550-smmu-500
568 then: 435 then:
569 properties: 436 properties:
570 clock-names: false 437 clock-names: false
571 clocks: false 438 clocks: false
572 439
573 - if: 440 - if:
574 properties: 441 properties:
575 compatible: 442 compatible:
576 contains: 443 contains:
577 const: qcom,sm6375-smmu-500 444 const: qcom,sm6375-smmu-500
578 then: 445 then:
579 properties: 446 properties:
580 power-domains: 447 power-domains:
581 items: 448 items:
582 - description: SNoC MMU TBU RT GDS 449 - description: SNoC MMU TBU RT GDSC
583 - description: SNoC MMU TBU NRT GD 450 - description: SNoC MMU TBU NRT GDSC
584 - description: SNoC TURING MMU TBU 451 - description: SNoC TURING MMU TBU0 GDSC
585 452
586 required: 453 required:
587 - power-domains 454 - power-domains
588 else: 455 else:
589 properties: 456 properties:
590 power-domains: 457 power-domains:
591 maxItems: 1 458 maxItems: 1
592 459
593 examples: 460 examples:
594 - |+ 461 - |+
595 /* SMMU with stream matching or stream ind 462 /* SMMU with stream matching or stream indexing */
596 smmu1: iommu@ba5e0000 { 463 smmu1: iommu@ba5e0000 {
597 compatible = "arm,smmu-v1"; 464 compatible = "arm,smmu-v1";
598 reg = <0xba5e0000 0x10000>; 465 reg = <0xba5e0000 0x10000>;
599 #global-interrupts = <2>; 466 #global-interrupts = <2>;
600 interrupts = <0 32 4>, 467 interrupts = <0 32 4>,
601 <0 33 4>, 468 <0 33 4>,
602 <0 34 4>, /* This is 469 <0 34 4>, /* This is the first context interrupt */
603 <0 35 4>, 470 <0 35 4>,
604 <0 36 4>, 471 <0 36 4>,
605 <0 37 4>; 472 <0 37 4>;
606 #iommu-cells = <1>; 473 #iommu-cells = <1>;
607 }; 474 };
608 475
609 /* device with two stream IDs, 0 and 7 */ 476 /* device with two stream IDs, 0 and 7 */
610 master1 { 477 master1 {
611 iommus = <&smmu1 0>, 478 iommus = <&smmu1 0>,
612 <&smmu1 7>; 479 <&smmu1 7>;
613 }; 480 };
614 481
615 482
616 /* SMMU with stream matching */ 483 /* SMMU with stream matching */
617 smmu2: iommu@ba5f0000 { 484 smmu2: iommu@ba5f0000 {
618 compatible = "arm,smmu-v1"; 485 compatible = "arm,smmu-v1";
619 reg = <0xba5f0000 0x10000>; 486 reg = <0xba5f0000 0x10000>;
620 #global-interrupts = <2>; 487 #global-interrupts = <2>;
621 interrupts = <0 38 4>, 488 interrupts = <0 38 4>,
622 <0 39 4>, 489 <0 39 4>,
623 <0 40 4>, /* This is 490 <0 40 4>, /* This is the first context interrupt */
624 <0 41 4>, 491 <0 41 4>,
625 <0 42 4>, 492 <0 42 4>,
626 <0 43 4>; 493 <0 43 4>;
627 #iommu-cells = <2>; 494 #iommu-cells = <2>;
628 }; 495 };
629 496
630 /* device with stream IDs 0 and 7 */ 497 /* device with stream IDs 0 and 7 */
631 master2 { 498 master2 {
632 iommus = <&smmu2 0 0>, 499 iommus = <&smmu2 0 0>,
633 <&smmu2 7 0>; 500 <&smmu2 7 0>;
634 }; 501 };
635 502
636 /* device with stream IDs 1, 17, 33 and 49 503 /* device with stream IDs 1, 17, 33 and 49 */
637 master3 { 504 master3 {
638 iommus = <&smmu2 1 0x30>; 505 iommus = <&smmu2 1 0x30>;
639 }; 506 };
640 507
641 508
642 /* ARM MMU-500 with 10-bit stream ID input 509 /* ARM MMU-500 with 10-bit stream ID input configuration */
643 smmu3: iommu@ba600000 { 510 smmu3: iommu@ba600000 {
644 compatible = "arm,mmu-500", "arm,s 511 compatible = "arm,mmu-500", "arm,smmu-v2";
645 reg = <0xba600000 0x10000>; 512 reg = <0xba600000 0x10000>;
646 #global-interrupts = <2>; 513 #global-interrupts = <2>;
647 interrupts = <0 44 4>, 514 interrupts = <0 44 4>,
648 <0 45 4>, 515 <0 45 4>,
649 <0 46 4>, /* This is 516 <0 46 4>, /* This is the first context interrupt */
650 <0 47 4>, 517 <0 47 4>,
651 <0 48 4>, 518 <0 48 4>,
652 <0 49 4>; 519 <0 49 4>;
653 #iommu-cells = <1>; 520 #iommu-cells = <1>;
654 /* always ignore appended 5-bit TB 521 /* always ignore appended 5-bit TBU number */
655 stream-match-mask = <0x7c00>; 522 stream-match-mask = <0x7c00>;
656 }; 523 };
657 524
658 bus { 525 bus {
659 /* bus whose child devices emit on 526 /* bus whose child devices emit one unique 10-bit stream
660 ID each, but may master through 527 ID each, but may master through multiple SMMU TBUs */
661 iommu-map = <0 &smmu3 0 0x400>; 528 iommu-map = <0 &smmu3 0 0x400>;
662 529
663 530
664 }; 531 };
665 532
666 - |+ 533 - |+
667 /* Qcom's arm,smmu-v2 implementation */ 534 /* Qcom's arm,smmu-v2 implementation */
668 #include <dt-bindings/interrupt-controller 535 #include <dt-bindings/interrupt-controller/arm-gic.h>
669 #include <dt-bindings/interrupt-controller 536 #include <dt-bindings/interrupt-controller/irq.h>
670 smmu4: iommu@d00000 { 537 smmu4: iommu@d00000 {
671 compatible = "qcom,msm8996-smmu-v2", "qc 538 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
672 reg = <0xd00000 0x10000>; 539 reg = <0xd00000 0x10000>;
673 540
674 #global-interrupts = <1>; 541 #global-interrupts = <1>;
675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_ 542 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH> 543 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH> 544 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
678 #iommu-cells = <1>; 545 #iommu-cells = <1>;
679 power-domains = <&mmcc 0>; 546 power-domains = <&mmcc 0>;
680 547
681 clocks = <&mmcc 123>, 548 clocks = <&mmcc 123>,
682 <&mmcc 124>; 549 <&mmcc 124>;
683 clock-names = "bus", "iface"; 550 clock-names = "bus", "iface";
684 }; 551 };
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