1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,s 4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM System MMU Architecture Implementat 7 title: ARM System MMU Architecture Implementation
8 8
9 maintainers: 9 maintainers:
10 - Will Deacon <will@kernel.org> 10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com> 11 - Robin Murphy <Robin.Murphy@arm.com>
12 12
13 description: |+ 13 description: |+
14 ARM SoCs may contain an implementation of th 14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be u 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters extern 16 of address translation to bus masters external to the CPU.
17 17
18 The SMMU may also raise interrupts in respon 18 The SMMU may also raise interrupts in response to various fault
19 conditions. 19 conditions.
20 20
21 properties: 21 properties:
22 $nodename: 22 $nodename:
23 pattern: "^iommu@[0-9a-f]*" 23 pattern: "^iommu@[0-9a-f]*"
24 compatible: 24 compatible:
25 oneOf: 25 oneOf:
26 - description: Qcom SoCs implementing "a 26 - description: Qcom SoCs implementing "arm,smmu-v2"
27 items: 27 items:
28 - enum: 28 - enum:
29 - qcom,msm8996-smmu-v2 29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2 30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2 31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2 32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2 33 - const: qcom,smmu-v2
34 34
35 - description: Qcom SoCs implementing "q 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36 items: 36 items:
37 - enum: 37 - enum:
38 - qcom,qcm2290-smmu-500 38 - qcom,qcm2290-smmu-500
39 - qcom,qcs8300-smmu-500 <<
40 - qcom,qdu1000-smmu-500 39 - qcom,qdu1000-smmu-500
41 - qcom,sa8255p-smmu-500 <<
42 - qcom,sa8775p-smmu-500 40 - qcom,sa8775p-smmu-500
43 - qcom,sc7180-smmu-500 41 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500 42 - qcom,sc7280-smmu-500
45 - qcom,sc8180x-smmu-500 43 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500 44 - qcom,sc8280xp-smmu-500
47 - qcom,sdm670-smmu-500 45 - qcom,sdm670-smmu-500
48 - qcom,sdm845-smmu-500 46 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500 47 - qcom,sdx55-smmu-500
50 - qcom,sdx65-smmu-500 48 - qcom,sdx65-smmu-500
51 - qcom,sdx75-smmu-500 49 - qcom,sdx75-smmu-500
52 - qcom,sm6115-smmu-500 50 - qcom,sm6115-smmu-500
53 - qcom,sm6125-smmu-500 51 - qcom,sm6125-smmu-500
54 - qcom,sm6350-smmu-500 52 - qcom,sm6350-smmu-500
55 - qcom,sm6375-smmu-500 53 - qcom,sm6375-smmu-500
56 - qcom,sm8150-smmu-500 54 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500 55 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500 56 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500 57 - qcom,sm8450-smmu-500
60 - qcom,sm8550-smmu-500 58 - qcom,sm8550-smmu-500
61 - qcom,sm8650-smmu-500 <<
62 - qcom,x1e80100-smmu-500 <<
63 - const: qcom,smmu-500 59 - const: qcom,smmu-500
64 - const: arm,mmu-500 60 - const: arm,mmu-500
65 61
66 - description: Qcom SoCs implementing "a 62 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
67 deprecated: true 63 deprecated: true
68 items: 64 items:
69 # Do not add additional SoC to this 65 # Do not add additional SoC to this list. Instead use two previous lists.
70 - enum: 66 - enum:
71 - qcom,qcm2290-smmu-500 67 - qcom,qcm2290-smmu-500
72 - qcom,sc7180-smmu-500 68 - qcom,sc7180-smmu-500
73 - qcom,sc7280-smmu-500 69 - qcom,sc7280-smmu-500
74 - qcom,sc8180x-smmu-500 70 - qcom,sc8180x-smmu-500
75 - qcom,sc8280xp-smmu-500 71 - qcom,sc8280xp-smmu-500
76 - qcom,sdm845-smmu-500 72 - qcom,sdm845-smmu-500
77 - qcom,sm6115-smmu-500 73 - qcom,sm6115-smmu-500
78 - qcom,sm6350-smmu-500 74 - qcom,sm6350-smmu-500
79 - qcom,sm6375-smmu-500 75 - qcom,sm6375-smmu-500
80 - qcom,sm8150-smmu-500 76 - qcom,sm8150-smmu-500
81 - qcom,sm8250-smmu-500 77 - qcom,sm8250-smmu-500
82 - qcom,sm8350-smmu-500 78 - qcom,sm8350-smmu-500
83 - qcom,sm8450-smmu-500 79 - qcom,sm8450-smmu-500
84 - const: arm,mmu-500 80 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implemen 81 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
86 items: 82 items:
87 - enum: 83 - enum:
88 - qcom,qcm2290-smmu-500 <<
89 - qcom,sa8255p-smmu-500 <<
90 - qcom,sa8775p-smmu-500 84 - qcom,sa8775p-smmu-500
91 - qcom,sc7280-smmu-500 85 - qcom,sc7280-smmu-500
92 - qcom,sc8180x-smmu-500 <<
93 - qcom,sc8280xp-smmu-500 86 - qcom,sc8280xp-smmu-500
94 - qcom,sm6115-smmu-500 87 - qcom,sm6115-smmu-500
95 - qcom,sm6125-smmu-500 88 - qcom,sm6125-smmu-500
96 - qcom,sm8150-smmu-500 89 - qcom,sm8150-smmu-500
97 - qcom,sm8250-smmu-500 90 - qcom,sm8250-smmu-500
98 - qcom,sm8350-smmu-500 91 - qcom,sm8350-smmu-500
99 - qcom,sm8450-smmu-500 <<
100 - qcom,sm8550-smmu-500 <<
101 - qcom,sm8650-smmu-500 <<
102 - qcom,x1e80100-smmu-500 <<
103 - const: qcom,adreno-smmu 92 - const: qcom,adreno-smmu
104 - const: qcom,smmu-500 93 - const: qcom,smmu-500
105 - const: arm,mmu-500 94 - const: arm,mmu-500
106 - description: Qcom Adreno GPUs implemen 95 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
107 deprecated: true 96 deprecated: true
108 items: 97 items:
109 # Do not add additional SoC to this 98 # Do not add additional SoC to this list. Instead use previous list.
110 - enum: 99 - enum:
111 - qcom,sc7280-smmu-500 100 - qcom,sc7280-smmu-500
112 - qcom,sm8150-smmu-500 101 - qcom,sm8150-smmu-500
113 - qcom,sm8250-smmu-500 102 - qcom,sm8250-smmu-500
114 - const: qcom,adreno-smmu 103 - const: qcom,adreno-smmu
115 - const: arm,mmu-500 104 - const: arm,mmu-500
116 - description: Qcom Adreno GPUs implemen 105 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
117 items: 106 items:
118 - enum: 107 - enum:
119 - qcom,msm8996-smmu-v2 108 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2 109 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2 110 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2 111 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2 112 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2 113 - qcom,sm7150-smmu-v2
125 - const: qcom,adreno-smmu 114 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2 115 - const: qcom,smmu-v2
127 - description: Qcom Adreno GPUs on Googl 116 - description: Qcom Adreno GPUs on Google Cheza platform
128 items: 117 items:
129 - const: qcom,sdm845-smmu-v2 118 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2 119 - const: qcom,smmu-v2
131 - description: Marvell SoCs implementing 120 - description: Marvell SoCs implementing "arm,mmu-500"
132 items: 121 items:
133 - const: marvell,ap806-smmu-500 122 - const: marvell,ap806-smmu-500
134 - const: arm,mmu-500 123 - const: arm,mmu-500
135 - description: NVIDIA SoCs that require 124 - description: NVIDIA SoCs that require memory controller interaction
136 and may program multiple ARM MMU-500 125 and may program multiple ARM MMU-500s identically with the memory
137 controller interleaving translations 126 controller interleaving translations between multiple instances
138 for improved performance. 127 for improved performance.
139 items: 128 items:
140 - enum: 129 - enum:
141 - nvidia,tegra186-smmu 130 - nvidia,tegra186-smmu
142 - nvidia,tegra194-smmu 131 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu 132 - nvidia,tegra234-smmu
144 - const: nvidia,smmu-500 133 - const: nvidia,smmu-500
145 - items: 134 - items:
146 - const: arm,mmu-500 135 - const: arm,mmu-500
147 - const: arm,smmu-v2 136 - const: arm,smmu-v2
148 - items: 137 - items:
149 - enum: 138 - enum:
150 - arm,mmu-400 139 - arm,mmu-400
151 - arm,mmu-401 140 - arm,mmu-401
152 - const: arm,smmu-v1 141 - const: arm,smmu-v1
153 - enum: 142 - enum:
154 - arm,smmu-v1 143 - arm,smmu-v1
155 - arm,smmu-v2 144 - arm,smmu-v2
156 - arm,mmu-400 145 - arm,mmu-400
157 - arm,mmu-401 146 - arm,mmu-401
158 - arm,mmu-500 147 - arm,mmu-500
159 - cavium,smmu-v2 148 - cavium,smmu-v2
160 149
161 reg: 150 reg:
162 minItems: 1 151 minItems: 1
163 maxItems: 2 152 maxItems: 2
164 153
165 '#global-interrupts': 154 '#global-interrupts':
166 description: The number of global interrup 155 description: The number of global interrupts exposed by the device.
167 $ref: /schemas/types.yaml#/definitions/uin 156 $ref: /schemas/types.yaml#/definitions/uint32
168 minimum: 0 157 minimum: 0
169 maximum: 260 # 2 secure, 2 non-secure, a 158 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
170 159
171 '#iommu-cells': 160 '#iommu-cells':
172 enum: [ 1, 2 ] 161 enum: [ 1, 2 ]
173 description: | 162 description: |
174 See Documentation/devicetree/bindings/io 163 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
175 value of 1, each IOMMU specifier represe 164 value of 1, each IOMMU specifier represents a distinct stream ID emitted
176 by that device into the relevant SMMU. 165 by that device into the relevant SMMU.
177 166
178 SMMUs with stream matching support and c 167 SMMUs with stream matching support and complex masters may use a value of
179 2, where the second cell of the IOMMU sp 168 2, where the second cell of the IOMMU specifier represents an SMR mask to
180 combine with the ID in the first cell. 169 combine with the ID in the first cell. Care must be taken to ensure the
181 set of matched IDs does not result in co 170 set of matched IDs does not result in conflicts.
182 171
183 interrupts: 172 interrupts:
184 minItems: 1 173 minItems: 1
185 maxItems: 388 # 260 plus 128 contexts 174 maxItems: 388 # 260 plus 128 contexts
186 description: | 175 description: |
187 Interrupt list, with the first #global-i 176 Interrupt list, with the first #global-interrupts entries corresponding to
188 the global interrupts and any following 177 the global interrupts and any following entries corresponding to context
189 interrupts, specified in order of their 178 interrupts, specified in order of their indexing by the SMMU.
190 179
191 For SMMUv2 implementations, there must b 180 For SMMUv2 implementations, there must be exactly one interrupt per
192 context bank. In the case of a single, c 181 context bank. In the case of a single, combined interrupt, it must be
193 listed multiple times. 182 listed multiple times.
194 183
195 dma-coherent: 184 dma-coherent:
196 description: | 185 description: |
197 Present if page table walks made by the 186 Present if page table walks made by the SMMU are cache coherent with the
198 CPU. 187 CPU.
199 188
200 NOTE: this only applies to the SMMU itse 189 NOTE: this only applies to the SMMU itself, not masters connected
201 upstream of the SMMU. 190 upstream of the SMMU.
202 191
203 calxeda,smmu-secure-config-access: 192 calxeda,smmu-secure-config-access:
204 type: boolean 193 type: boolean
205 description: 194 description:
206 Enable proper handling of buggy implemen 195 Enable proper handling of buggy implementations that always use secure
207 access to SMMU configuration registers. 196 access to SMMU configuration registers. In this case non-secure aliases of
208 secure registers have to be used during 197 secure registers have to be used during SMMU configuration.
209 198
210 stream-match-mask: 199 stream-match-mask:
211 $ref: /schemas/types.yaml#/definitions/uin 200 $ref: /schemas/types.yaml#/definitions/uint32
212 description: | 201 description: |
213 For SMMUs supporting stream matching and 202 For SMMUs supporting stream matching and using #iommu-cells = <1>,
214 specifies a mask of bits to ignore when 203 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
215 be programmed into the SMRn.MASK field o 204 be programmed into the SMRn.MASK field of every stream match register
216 used). For cases where it is desirable t 205 used). For cases where it is desirable to ignore some portion of every
217 Stream ID (e.g. for certain MMU-500 conf 206 Stream ID (e.g. for certain MMU-500 configurations given globally unique
218 input IDs). This property is not valid f 207 input IDs). This property is not valid for SMMUs using stream indexing, or
219 using stream matching with #iommu-cells 208 using stream matching with #iommu-cells = <2>, and may be ignored if
220 present in such cases. 209 present in such cases.
221 210
222 clock-names: 211 clock-names:
223 minItems: 1 212 minItems: 1
224 maxItems: 7 213 maxItems: 7
225 214
226 clocks: 215 clocks:
227 minItems: 1 216 minItems: 1
228 maxItems: 7 217 maxItems: 7
229 218
230 power-domains: 219 power-domains:
231 minItems: 1 220 minItems: 1
232 maxItems: 3 221 maxItems: 3
233 222
234 nvidia,memory-controller: 223 nvidia,memory-controller:
235 description: | 224 description: |
236 A phandle to the memory controller on NV 225 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
237 The memory controller needs to be progra 226 The memory controller needs to be programmed with a mapping of memory
238 client IDs to ARM SMMU stream IDs. 227 client IDs to ARM SMMU stream IDs.
239 228
240 If this property is absent, the mapping 229 If this property is absent, the mapping programmed by early firmware
241 will be used and it is not guaranteed th 230 will be used and it is not guaranteed that IOMMU translations will be
242 enabled for any given device. 231 enabled for any given device.
243 $ref: /schemas/types.yaml#/definitions/pha 232 $ref: /schemas/types.yaml#/definitions/phandle
244 233
245 required: 234 required:
246 - compatible 235 - compatible
247 - reg 236 - reg
248 - '#global-interrupts' 237 - '#global-interrupts'
249 - '#iommu-cells' 238 - '#iommu-cells'
250 - interrupts 239 - interrupts
251 240
252 additionalProperties: false 241 additionalProperties: false
253 242
254 allOf: 243 allOf:
255 - if: 244 - if:
256 properties: 245 properties:
257 compatible: 246 compatible:
258 contains: 247 contains:
259 enum: 248 enum:
260 - nvidia,tegra186-smmu 249 - nvidia,tegra186-smmu
261 - nvidia,tegra194-smmu 250 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu 251 - nvidia,tegra234-smmu
263 then: 252 then:
264 properties: 253 properties:
265 reg: 254 reg:
266 minItems: 1 255 minItems: 1
267 maxItems: 2 256 maxItems: 2
268 257
269 # The reference to the memory controller 258 # The reference to the memory controller is required to ensure that the
270 # memory client to stream ID mapping can 259 # memory client to stream ID mapping can be done synchronously with the
271 # IOMMU attachment. 260 # IOMMU attachment.
272 required: 261 required:
273 - nvidia,memory-controller 262 - nvidia,memory-controller
274 else: 263 else:
275 properties: 264 properties:
276 reg: 265 reg:
277 maxItems: 1 266 maxItems: 1
278 267
279 - if: 268 - if:
280 properties: 269 properties:
281 compatible: 270 compatible:
282 contains: 271 contains:
283 enum: 272 enum:
284 - qcom,msm8998-smmu-v2 273 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2 274 - qcom,sdm630-smmu-v2
286 then: 275 then:
287 anyOf: 276 anyOf:
288 - properties: 277 - properties:
289 clock-names: 278 clock-names:
290 items: 279 items:
291 - const: bus 280 - const: bus
292 clocks: 281 clocks:
293 items: 282 items:
294 - description: bus clock requi 283 - description: bus clock required for downstream bus access and for
295 the smmu ptw 284 the smmu ptw
296 - properties: 285 - properties:
297 clock-names: 286 clock-names:
298 items: 287 items:
299 - const: iface 288 - const: iface
300 - const: mem 289 - const: mem
301 - const: mem_iface 290 - const: mem_iface
302 clocks: 291 clocks:
303 items: 292 items:
304 - description: interface clock 293 - description: interface clock required to access smmu's registers
305 through the TCU's programm 294 through the TCU's programming interface.
306 - description: bus clock requi 295 - description: bus clock required for memory access
307 - description: bus clock requi 296 - description: bus clock required for GPU memory access
308 - properties: 297 - properties:
309 clock-names: 298 clock-names:
310 items: 299 items:
311 - const: iface-mm 300 - const: iface-mm
312 - const: iface-smmu 301 - const: iface-smmu
313 - const: bus-smmu 302 - const: bus-smmu
314 clocks: 303 clocks:
315 items: 304 items:
316 - description: interface clock 305 - description: interface clock required to access mnoc's registers
317 through the TCU's programm 306 through the TCU's programming interface.
318 - description: interface clock 307 - description: interface clock required to access smmu's registers
319 through the TCU's programm 308 through the TCU's programming interface.
320 - description: bus clock requi 309 - description: bus clock required for the smmu ptw
321 310
322 - if: 311 - if:
323 properties: 312 properties:
324 compatible: 313 compatible:
325 contains: 314 contains:
326 enum: 315 enum:
327 - qcom,sm6375-smmu-v2 316 - qcom,sm6375-smmu-v2
328 then: 317 then:
329 anyOf: 318 anyOf:
330 - properties: 319 - properties:
331 clock-names: 320 clock-names:
332 items: 321 items:
333 - const: bus 322 - const: bus
334 clocks: 323 clocks:
335 items: 324 items:
336 - description: bus clock requi 325 - description: bus clock required for downstream bus access and for
337 the smmu ptw 326 the smmu ptw
338 - properties: 327 - properties:
339 clock-names: 328 clock-names:
340 items: 329 items:
341 - const: iface 330 - const: iface
342 - const: mem 331 - const: mem
343 - const: mem_iface 332 - const: mem_iface
344 clocks: 333 clocks:
345 items: 334 items:
346 - description: interface clock 335 - description: interface clock required to access smmu's registers
347 through the TCU's programm 336 through the TCU's programming interface.
348 - description: bus clock requi 337 - description: bus clock required for memory access
349 - description: bus clock requi 338 - description: bus clock required for GPU memory access
350 - properties: 339 - properties:
351 clock-names: 340 clock-names:
352 items: 341 items:
353 - const: iface-mm 342 - const: iface-mm
354 - const: iface-smmu 343 - const: iface-smmu
355 - const: bus-mm 344 - const: bus-mm
356 - const: bus-smmu 345 - const: bus-smmu
357 clocks: 346 clocks:
358 items: 347 items:
359 - description: interface clock 348 - description: interface clock required to access mnoc's registers
360 through the TCU's programm 349 through the TCU's programming interface.
361 - description: interface clock 350 - description: interface clock required to access smmu's registers
362 through the TCU's programm 351 through the TCU's programming interface.
363 - description: bus clock requi 352 - description: bus clock required for downstream bus access
364 - description: bus clock requi 353 - description: bus clock required for the smmu ptw
365 354
366 - if: 355 - if:
367 properties: 356 properties:
368 compatible: 357 compatible:
369 contains: 358 contains:
370 enum: 359 enum:
371 - qcom,msm8996-smmu-v2 360 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2 361 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2 362 - qcom,sdm845-smmu-v2
374 then: 363 then:
375 properties: 364 properties:
376 clock-names: 365 clock-names:
377 items: 366 items:
378 - const: bus 367 - const: bus
379 - const: iface 368 - const: iface
380 369
381 clocks: 370 clocks:
382 items: 371 items:
383 - description: bus clock required 372 - description: bus clock required for downstream bus access and for
384 the smmu ptw 373 the smmu ptw
385 - description: interface clock req 374 - description: interface clock required to access smmu's registers
386 through the TCU's programming 375 through the TCU's programming interface.
387 376
388 - if: 377 - if:
389 properties: 378 properties:
390 compatible: 379 compatible:
391 contains: 380 contains:
392 enum: 381 enum:
393 - qcom,sa8775p-smmu-500 382 - qcom,sa8775p-smmu-500
394 - qcom,sc7280-smmu-500 383 - qcom,sc7280-smmu-500
395 - qcom,sc8280xp-smmu-500 384 - qcom,sc8280xp-smmu-500
396 then: 385 then:
397 properties: 386 properties:
398 clock-names: 387 clock-names:
399 items: 388 items:
400 - const: gcc_gpu_memnoc_gfx_clk 389 - const: gcc_gpu_memnoc_gfx_clk
401 - const: gcc_gpu_snoc_dvm_gfx_clk 390 - const: gcc_gpu_snoc_dvm_gfx_clk
402 - const: gpu_cc_ahb_clk 391 - const: gpu_cc_ahb_clk
403 - const: gpu_cc_hlos1_vote_gpu_smm 392 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
404 - const: gpu_cc_cx_gmu_clk 393 - const: gpu_cc_cx_gmu_clk
405 - const: gpu_cc_hub_cx_int_clk 394 - const: gpu_cc_hub_cx_int_clk
406 - const: gpu_cc_hub_aon_clk 395 - const: gpu_cc_hub_aon_clk
407 396
408 clocks: 397 clocks:
409 items: 398 items:
410 - description: GPU memnoc_gfx cloc 399 - description: GPU memnoc_gfx clock
411 - description: GPU snoc_dvm_gfx cl 400 - description: GPU snoc_dvm_gfx clock
412 - description: GPU ahb clock 401 - description: GPU ahb clock
413 - description: GPU hlos1_vote_GPU 402 - description: GPU hlos1_vote_GPU smmu clock
414 - description: GPU cx_gmu clock 403 - description: GPU cx_gmu clock
415 - description: GPU hub_cx_int cloc 404 - description: GPU hub_cx_int clock
416 - description: GPU hub_aon clock 405 - description: GPU hub_aon clock
417 406
418 - if: 407 - if:
419 properties: 408 properties:
420 compatible: 409 compatible:
421 contains: 410 contains:
422 enum: 411 enum:
423 - qcom,sc8180x-smmu-500 <<
424 - qcom,sm6350-smmu-v2 412 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2 413 - qcom,sm7150-smmu-v2
426 - qcom,sm8150-smmu-500 414 - qcom,sm8150-smmu-500
427 - qcom,sm8250-smmu-500 415 - qcom,sm8250-smmu-500
428 then: 416 then:
429 properties: 417 properties:
430 clock-names: 418 clock-names:
431 items: 419 items:
432 - const: ahb 420 - const: ahb
433 - const: bus 421 - const: bus
434 - const: iface 422 - const: iface
435 423
436 clocks: 424 clocks:
437 items: 425 items:
438 - description: bus clock required 426 - description: bus clock required for AHB bus access
439 - description: bus clock required 427 - description: bus clock required for downstream bus access and for
440 the smmu ptw 428 the smmu ptw
441 - description: interface clock req 429 - description: interface clock required to access smmu's registers
442 through the TCU's programming 430 through the TCU's programming interface.
443 431
444 - if: 432 - if:
445 properties: 433 properties:
446 compatible: 434 compatible:
447 items: 435 items:
448 - enum: 436 - enum:
449 - qcom,sm8350-smmu-500 <<
450 - const: qcom,adreno-smmu <<
451 - const: qcom,smmu-500 <<
452 - const: arm,mmu-500 <<
453 then: <<
454 properties: <<
455 clock-names: <<
456 items: <<
457 - const: bus <<
458 - const: iface <<
459 - const: ahb <<
460 - const: hlos1_vote_gpu_smmu <<
461 - const: cx_gmu <<
462 - const: hub_cx_int <<
463 - const: hub_aon <<
464 clocks: <<
465 minItems: 7 <<
466 maxItems: 7 <<
467 <<
468 - if: <<
469 properties: <<
470 compatible: <<
471 items: <<
472 - enum: <<
473 - qcom,qcm2290-smmu-500 <<
474 - qcom,sm6115-smmu-500 437 - qcom,sm6115-smmu-500
475 - qcom,sm6125-smmu-500 438 - qcom,sm6125-smmu-500
476 - const: qcom,adreno-smmu 439 - const: qcom,adreno-smmu
477 - const: qcom,smmu-500 440 - const: qcom,smmu-500
478 - const: arm,mmu-500 441 - const: arm,mmu-500
479 then: 442 then:
480 properties: 443 properties:
481 clock-names: 444 clock-names:
482 items: 445 items:
483 - const: mem 446 - const: mem
484 - const: hlos 447 - const: hlos
485 - const: iface 448 - const: iface
486 449
487 clocks: 450 clocks:
488 items: 451 items:
489 - description: GPU memory bus cloc 452 - description: GPU memory bus clock
490 - description: Voter clock require 453 - description: Voter clock required for HLOS SMMU access
491 - description: Interface clock req 454 - description: Interface clock required for register access
492 455
493 - if: <<
494 properties: <<
495 compatible: <<
496 items: <<
497 - const: qcom,sm8450-smmu-500 <<
498 - const: qcom,adreno-smmu <<
499 - const: qcom,smmu-500 <<
500 - const: arm,mmu-500 <<
501 <<
502 then: <<
503 properties: <<
504 clock-names: <<
505 items: <<
506 - const: gmu <<
507 - const: hub <<
508 - const: hlos <<
509 - const: bus <<
510 - const: iface <<
511 - const: ahb <<
512 <<
513 clocks: <<
514 items: <<
515 - description: GMU clock <<
516 - description: GPU HUB clock <<
517 - description: HLOS vote clock <<
518 - description: GPU memory bus cloc <<
519 - description: GPU SNoC bus clock <<
520 - description: GPU AHB clock <<
521 <<
522 - if: <<
523 properties: <<
524 compatible: <<
525 items: <<
526 - enum: <<
527 - qcom,sm8550-smmu-500 <<
528 - qcom,sm8650-smmu-500 <<
529 - qcom,x1e80100-smmu-500 <<
530 - const: qcom,adreno-smmu <<
531 - const: qcom,smmu-500 <<
532 - const: arm,mmu-500 <<
533 then: <<
534 properties: <<
535 clock-names: <<
536 items: <<
537 - const: hlos <<
538 - const: bus <<
539 - const: iface <<
540 - const: ahb <<
541 <<
542 clocks: <<
543 items: <<
544 - description: HLOS vote clock <<
545 - description: GPU memory bus cloc <<
546 - description: GPU SNoC bus clock <<
547 - description: GPU AHB clock <<
548 <<
549 # Disallow clocks for all other platforms wi 456 # Disallow clocks for all other platforms with specific compatibles
550 - if: 457 - if:
551 properties: 458 properties:
552 compatible: 459 compatible:
553 contains: 460 contains:
554 enum: 461 enum:
555 - cavium,smmu-v2 462 - cavium,smmu-v2
556 - marvell,ap806-smmu-500 463 - marvell,ap806-smmu-500
557 - nvidia,smmu-500 464 - nvidia,smmu-500
558 - qcom,qcs8300-smmu-500 !! 465 - qcom,qcm2290-smmu-500
559 - qcom,qdu1000-smmu-500 466 - qcom,qdu1000-smmu-500
560 - qcom,sa8255p-smmu-500 <<
561 - qcom,sc7180-smmu-500 467 - qcom,sc7180-smmu-500
>> 468 - qcom,sc8180x-smmu-500
562 - qcom,sdm670-smmu-500 469 - qcom,sdm670-smmu-500
563 - qcom,sdm845-smmu-500 470 - qcom,sdm845-smmu-500
564 - qcom,sdx55-smmu-500 471 - qcom,sdx55-smmu-500
565 - qcom,sdx65-smmu-500 472 - qcom,sdx65-smmu-500
566 - qcom,sm6350-smmu-500 473 - qcom,sm6350-smmu-500
567 - qcom,sm6375-smmu-500 474 - qcom,sm6375-smmu-500
>> 475 - qcom,sm8350-smmu-500
>> 476 - qcom,sm8450-smmu-500
>> 477 - qcom,sm8550-smmu-500
568 then: 478 then:
569 properties: 479 properties:
570 clock-names: false 480 clock-names: false
571 clocks: false 481 clocks: false
572 482
573 - if: 483 - if:
574 properties: 484 properties:
575 compatible: 485 compatible:
576 contains: 486 contains:
577 const: qcom,sm6375-smmu-500 487 const: qcom,sm6375-smmu-500
578 then: 488 then:
579 properties: 489 properties:
580 power-domains: 490 power-domains:
581 items: 491 items:
582 - description: SNoC MMU TBU RT GDS 492 - description: SNoC MMU TBU RT GDSC
583 - description: SNoC MMU TBU NRT GD 493 - description: SNoC MMU TBU NRT GDSC
584 - description: SNoC TURING MMU TBU 494 - description: SNoC TURING MMU TBU0 GDSC
585 495
586 required: 496 required:
587 - power-domains 497 - power-domains
588 else: 498 else:
589 properties: 499 properties:
590 power-domains: 500 power-domains:
591 maxItems: 1 501 maxItems: 1
592 502
593 examples: 503 examples:
594 - |+ 504 - |+
595 /* SMMU with stream matching or stream ind 505 /* SMMU with stream matching or stream indexing */
596 smmu1: iommu@ba5e0000 { 506 smmu1: iommu@ba5e0000 {
597 compatible = "arm,smmu-v1"; 507 compatible = "arm,smmu-v1";
598 reg = <0xba5e0000 0x10000>; 508 reg = <0xba5e0000 0x10000>;
599 #global-interrupts = <2>; 509 #global-interrupts = <2>;
600 interrupts = <0 32 4>, 510 interrupts = <0 32 4>,
601 <0 33 4>, 511 <0 33 4>,
602 <0 34 4>, /* This is 512 <0 34 4>, /* This is the first context interrupt */
603 <0 35 4>, 513 <0 35 4>,
604 <0 36 4>, 514 <0 36 4>,
605 <0 37 4>; 515 <0 37 4>;
606 #iommu-cells = <1>; 516 #iommu-cells = <1>;
607 }; 517 };
608 518
609 /* device with two stream IDs, 0 and 7 */ 519 /* device with two stream IDs, 0 and 7 */
610 master1 { 520 master1 {
611 iommus = <&smmu1 0>, 521 iommus = <&smmu1 0>,
612 <&smmu1 7>; 522 <&smmu1 7>;
613 }; 523 };
614 524
615 525
616 /* SMMU with stream matching */ 526 /* SMMU with stream matching */
617 smmu2: iommu@ba5f0000 { 527 smmu2: iommu@ba5f0000 {
618 compatible = "arm,smmu-v1"; 528 compatible = "arm,smmu-v1";
619 reg = <0xba5f0000 0x10000>; 529 reg = <0xba5f0000 0x10000>;
620 #global-interrupts = <2>; 530 #global-interrupts = <2>;
621 interrupts = <0 38 4>, 531 interrupts = <0 38 4>,
622 <0 39 4>, 532 <0 39 4>,
623 <0 40 4>, /* This is 533 <0 40 4>, /* This is the first context interrupt */
624 <0 41 4>, 534 <0 41 4>,
625 <0 42 4>, 535 <0 42 4>,
626 <0 43 4>; 536 <0 43 4>;
627 #iommu-cells = <2>; 537 #iommu-cells = <2>;
628 }; 538 };
629 539
630 /* device with stream IDs 0 and 7 */ 540 /* device with stream IDs 0 and 7 */
631 master2 { 541 master2 {
632 iommus = <&smmu2 0 0>, 542 iommus = <&smmu2 0 0>,
633 <&smmu2 7 0>; 543 <&smmu2 7 0>;
634 }; 544 };
635 545
636 /* device with stream IDs 1, 17, 33 and 49 546 /* device with stream IDs 1, 17, 33 and 49 */
637 master3 { 547 master3 {
638 iommus = <&smmu2 1 0x30>; 548 iommus = <&smmu2 1 0x30>;
639 }; 549 };
640 550
641 551
642 /* ARM MMU-500 with 10-bit stream ID input 552 /* ARM MMU-500 with 10-bit stream ID input configuration */
643 smmu3: iommu@ba600000 { 553 smmu3: iommu@ba600000 {
644 compatible = "arm,mmu-500", "arm,s 554 compatible = "arm,mmu-500", "arm,smmu-v2";
645 reg = <0xba600000 0x10000>; 555 reg = <0xba600000 0x10000>;
646 #global-interrupts = <2>; 556 #global-interrupts = <2>;
647 interrupts = <0 44 4>, 557 interrupts = <0 44 4>,
648 <0 45 4>, 558 <0 45 4>,
649 <0 46 4>, /* This is 559 <0 46 4>, /* This is the first context interrupt */
650 <0 47 4>, 560 <0 47 4>,
651 <0 48 4>, 561 <0 48 4>,
652 <0 49 4>; 562 <0 49 4>;
653 #iommu-cells = <1>; 563 #iommu-cells = <1>;
654 /* always ignore appended 5-bit TB 564 /* always ignore appended 5-bit TBU number */
655 stream-match-mask = <0x7c00>; 565 stream-match-mask = <0x7c00>;
656 }; 566 };
657 567
658 bus { 568 bus {
659 /* bus whose child devices emit on 569 /* bus whose child devices emit one unique 10-bit stream
660 ID each, but may master through 570 ID each, but may master through multiple SMMU TBUs */
661 iommu-map = <0 &smmu3 0 0x400>; 571 iommu-map = <0 &smmu3 0 0x400>;
662 572
663 573
664 }; 574 };
665 575
666 - |+ 576 - |+
667 /* Qcom's arm,smmu-v2 implementation */ 577 /* Qcom's arm,smmu-v2 implementation */
668 #include <dt-bindings/interrupt-controller 578 #include <dt-bindings/interrupt-controller/arm-gic.h>
669 #include <dt-bindings/interrupt-controller 579 #include <dt-bindings/interrupt-controller/irq.h>
670 smmu4: iommu@d00000 { 580 smmu4: iommu@d00000 {
671 compatible = "qcom,msm8996-smmu-v2", "qc 581 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
672 reg = <0xd00000 0x10000>; 582 reg = <0xd00000 0x10000>;
673 583
674 #global-interrupts = <1>; 584 #global-interrupts = <1>;
675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_ 585 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH> 586 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH> 587 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
678 #iommu-cells = <1>; 588 #iommu-cells = <1>;
679 power-domains = <&mmcc 0>; 589 power-domains = <&mmcc 0>;
680 590
681 clocks = <&mmcc 123>, 591 clocks = <&mmcc 123>,
682 <&mmcc 124>; 592 <&mmcc 124>;
683 clock-names = "bus", "iface"; 593 clock-names = "bus", "iface";
684 }; 594 };
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