1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,s 4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM System MMU Architecture Implementat 7 title: ARM System MMU Architecture Implementation
8 8
9 maintainers: 9 maintainers:
10 - Will Deacon <will@kernel.org> 10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com> 11 - Robin Murphy <Robin.Murphy@arm.com>
12 12
13 description: |+ 13 description: |+
14 ARM SoCs may contain an implementation of th 14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be u 15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters extern 16 of address translation to bus masters external to the CPU.
17 17
18 The SMMU may also raise interrupts in respon 18 The SMMU may also raise interrupts in response to various fault
19 conditions. 19 conditions.
20 20
21 properties: 21 properties:
22 $nodename: 22 $nodename:
23 pattern: "^iommu@[0-9a-f]*" 23 pattern: "^iommu@[0-9a-f]*"
24 compatible: 24 compatible:
25 oneOf: 25 oneOf:
26 - description: Qcom SoCs implementing "a 26 - description: Qcom SoCs implementing "arm,smmu-v2"
27 items: 27 items:
28 - enum: 28 - enum:
29 - qcom,msm8996-smmu-v2 29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2 30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2 31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2 32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2 33 - const: qcom,smmu-v2
34 34
35 - description: Qcom SoCs implementing "q 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
36 items: 36 items:
37 - enum: 37 - enum:
38 - qcom,qcm2290-smmu-500 38 - qcom,qcm2290-smmu-500
39 - qcom,qcs8300-smmu-500 39 - qcom,qcs8300-smmu-500
40 - qcom,qdu1000-smmu-500 40 - qcom,qdu1000-smmu-500
41 - qcom,sa8255p-smmu-500 41 - qcom,sa8255p-smmu-500
42 - qcom,sa8775p-smmu-500 42 - qcom,sa8775p-smmu-500
43 - qcom,sc7180-smmu-500 43 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500 44 - qcom,sc7280-smmu-500
45 - qcom,sc8180x-smmu-500 45 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500 46 - qcom,sc8280xp-smmu-500
47 - qcom,sdm670-smmu-500 47 - qcom,sdm670-smmu-500
48 - qcom,sdm845-smmu-500 48 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500 49 - qcom,sdx55-smmu-500
50 - qcom,sdx65-smmu-500 50 - qcom,sdx65-smmu-500
51 - qcom,sdx75-smmu-500 51 - qcom,sdx75-smmu-500
52 - qcom,sm6115-smmu-500 52 - qcom,sm6115-smmu-500
53 - qcom,sm6125-smmu-500 53 - qcom,sm6125-smmu-500
54 - qcom,sm6350-smmu-500 54 - qcom,sm6350-smmu-500
55 - qcom,sm6375-smmu-500 55 - qcom,sm6375-smmu-500
56 - qcom,sm8150-smmu-500 56 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500 57 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500 58 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500 59 - qcom,sm8450-smmu-500
60 - qcom,sm8550-smmu-500 60 - qcom,sm8550-smmu-500
61 - qcom,sm8650-smmu-500 61 - qcom,sm8650-smmu-500
62 - qcom,x1e80100-smmu-500 62 - qcom,x1e80100-smmu-500
63 - const: qcom,smmu-500 63 - const: qcom,smmu-500
64 - const: arm,mmu-500 64 - const: arm,mmu-500
65 65
66 - description: Qcom SoCs implementing "a 66 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
67 deprecated: true 67 deprecated: true
68 items: 68 items:
69 # Do not add additional SoC to this 69 # Do not add additional SoC to this list. Instead use two previous lists.
70 - enum: 70 - enum:
71 - qcom,qcm2290-smmu-500 71 - qcom,qcm2290-smmu-500
72 - qcom,sc7180-smmu-500 72 - qcom,sc7180-smmu-500
73 - qcom,sc7280-smmu-500 73 - qcom,sc7280-smmu-500
74 - qcom,sc8180x-smmu-500 74 - qcom,sc8180x-smmu-500
75 - qcom,sc8280xp-smmu-500 75 - qcom,sc8280xp-smmu-500
76 - qcom,sdm845-smmu-500 76 - qcom,sdm845-smmu-500
77 - qcom,sm6115-smmu-500 77 - qcom,sm6115-smmu-500
78 - qcom,sm6350-smmu-500 78 - qcom,sm6350-smmu-500
79 - qcom,sm6375-smmu-500 79 - qcom,sm6375-smmu-500
80 - qcom,sm8150-smmu-500 80 - qcom,sm8150-smmu-500
81 - qcom,sm8250-smmu-500 81 - qcom,sm8250-smmu-500
82 - qcom,sm8350-smmu-500 82 - qcom,sm8350-smmu-500
83 - qcom,sm8450-smmu-500 83 - qcom,sm8450-smmu-500
84 - const: arm,mmu-500 84 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implemen 85 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
86 items: 86 items:
87 - enum: 87 - enum:
88 - qcom,qcm2290-smmu-500 88 - qcom,qcm2290-smmu-500
89 - qcom,sa8255p-smmu-500 89 - qcom,sa8255p-smmu-500
90 - qcom,sa8775p-smmu-500 90 - qcom,sa8775p-smmu-500
91 - qcom,sc7280-smmu-500 91 - qcom,sc7280-smmu-500
92 - qcom,sc8180x-smmu-500 92 - qcom,sc8180x-smmu-500
93 - qcom,sc8280xp-smmu-500 93 - qcom,sc8280xp-smmu-500
94 - qcom,sm6115-smmu-500 94 - qcom,sm6115-smmu-500
95 - qcom,sm6125-smmu-500 95 - qcom,sm6125-smmu-500
96 - qcom,sm8150-smmu-500 96 - qcom,sm8150-smmu-500
97 - qcom,sm8250-smmu-500 97 - qcom,sm8250-smmu-500
98 - qcom,sm8350-smmu-500 98 - qcom,sm8350-smmu-500
99 - qcom,sm8450-smmu-500 99 - qcom,sm8450-smmu-500
100 - qcom,sm8550-smmu-500 100 - qcom,sm8550-smmu-500
101 - qcom,sm8650-smmu-500 101 - qcom,sm8650-smmu-500
102 - qcom,x1e80100-smmu-500 102 - qcom,x1e80100-smmu-500
103 - const: qcom,adreno-smmu 103 - const: qcom,adreno-smmu
104 - const: qcom,smmu-500 104 - const: qcom,smmu-500
105 - const: arm,mmu-500 105 - const: arm,mmu-500
106 - description: Qcom Adreno GPUs implemen 106 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
107 deprecated: true 107 deprecated: true
108 items: 108 items:
109 # Do not add additional SoC to this 109 # Do not add additional SoC to this list. Instead use previous list.
110 - enum: 110 - enum:
111 - qcom,sc7280-smmu-500 111 - qcom,sc7280-smmu-500
112 - qcom,sm8150-smmu-500 112 - qcom,sm8150-smmu-500
113 - qcom,sm8250-smmu-500 113 - qcom,sm8250-smmu-500
114 - const: qcom,adreno-smmu 114 - const: qcom,adreno-smmu
115 - const: arm,mmu-500 115 - const: arm,mmu-500
116 - description: Qcom Adreno GPUs implemen 116 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
117 items: 117 items:
118 - enum: 118 - enum:
119 - qcom,msm8996-smmu-v2 119 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2 120 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2 121 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2 122 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2 123 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2 124 - qcom,sm7150-smmu-v2
125 - const: qcom,adreno-smmu 125 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2 126 - const: qcom,smmu-v2
127 - description: Qcom Adreno GPUs on Googl 127 - description: Qcom Adreno GPUs on Google Cheza platform
128 items: 128 items:
129 - const: qcom,sdm845-smmu-v2 129 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2 130 - const: qcom,smmu-v2
131 - description: Marvell SoCs implementing 131 - description: Marvell SoCs implementing "arm,mmu-500"
132 items: 132 items:
133 - const: marvell,ap806-smmu-500 133 - const: marvell,ap806-smmu-500
134 - const: arm,mmu-500 134 - const: arm,mmu-500
135 - description: NVIDIA SoCs that require 135 - description: NVIDIA SoCs that require memory controller interaction
136 and may program multiple ARM MMU-500 136 and may program multiple ARM MMU-500s identically with the memory
137 controller interleaving translations 137 controller interleaving translations between multiple instances
138 for improved performance. 138 for improved performance.
139 items: 139 items:
140 - enum: 140 - enum:
141 - nvidia,tegra186-smmu 141 - nvidia,tegra186-smmu
142 - nvidia,tegra194-smmu 142 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu 143 - nvidia,tegra234-smmu
144 - const: nvidia,smmu-500 144 - const: nvidia,smmu-500
145 - items: 145 - items:
146 - const: arm,mmu-500 146 - const: arm,mmu-500
147 - const: arm,smmu-v2 147 - const: arm,smmu-v2
148 - items: 148 - items:
149 - enum: 149 - enum:
150 - arm,mmu-400 150 - arm,mmu-400
151 - arm,mmu-401 151 - arm,mmu-401
152 - const: arm,smmu-v1 152 - const: arm,smmu-v1
153 - enum: 153 - enum:
154 - arm,smmu-v1 154 - arm,smmu-v1
155 - arm,smmu-v2 155 - arm,smmu-v2
156 - arm,mmu-400 156 - arm,mmu-400
157 - arm,mmu-401 157 - arm,mmu-401
158 - arm,mmu-500 158 - arm,mmu-500
159 - cavium,smmu-v2 159 - cavium,smmu-v2
160 160
161 reg: 161 reg:
162 minItems: 1 162 minItems: 1
163 maxItems: 2 163 maxItems: 2
164 164
165 '#global-interrupts': 165 '#global-interrupts':
166 description: The number of global interrup 166 description: The number of global interrupts exposed by the device.
167 $ref: /schemas/types.yaml#/definitions/uin 167 $ref: /schemas/types.yaml#/definitions/uint32
168 minimum: 0 168 minimum: 0
169 maximum: 260 # 2 secure, 2 non-secure, a 169 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
170 170
171 '#iommu-cells': 171 '#iommu-cells':
172 enum: [ 1, 2 ] 172 enum: [ 1, 2 ]
173 description: | 173 description: |
174 See Documentation/devicetree/bindings/io 174 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
175 value of 1, each IOMMU specifier represe 175 value of 1, each IOMMU specifier represents a distinct stream ID emitted
176 by that device into the relevant SMMU. 176 by that device into the relevant SMMU.
177 177
178 SMMUs with stream matching support and c 178 SMMUs with stream matching support and complex masters may use a value of
179 2, where the second cell of the IOMMU sp 179 2, where the second cell of the IOMMU specifier represents an SMR mask to
180 combine with the ID in the first cell. 180 combine with the ID in the first cell. Care must be taken to ensure the
181 set of matched IDs does not result in co 181 set of matched IDs does not result in conflicts.
182 182
183 interrupts: 183 interrupts:
184 minItems: 1 184 minItems: 1
185 maxItems: 388 # 260 plus 128 contexts 185 maxItems: 388 # 260 plus 128 contexts
186 description: | 186 description: |
187 Interrupt list, with the first #global-i 187 Interrupt list, with the first #global-interrupts entries corresponding to
188 the global interrupts and any following 188 the global interrupts and any following entries corresponding to context
189 interrupts, specified in order of their 189 interrupts, specified in order of their indexing by the SMMU.
190 190
191 For SMMUv2 implementations, there must b 191 For SMMUv2 implementations, there must be exactly one interrupt per
192 context bank. In the case of a single, c 192 context bank. In the case of a single, combined interrupt, it must be
193 listed multiple times. 193 listed multiple times.
194 194
195 dma-coherent: 195 dma-coherent:
196 description: | 196 description: |
197 Present if page table walks made by the 197 Present if page table walks made by the SMMU are cache coherent with the
198 CPU. 198 CPU.
199 199
200 NOTE: this only applies to the SMMU itse 200 NOTE: this only applies to the SMMU itself, not masters connected
201 upstream of the SMMU. 201 upstream of the SMMU.
202 202
203 calxeda,smmu-secure-config-access: 203 calxeda,smmu-secure-config-access:
204 type: boolean 204 type: boolean
205 description: 205 description:
206 Enable proper handling of buggy implemen 206 Enable proper handling of buggy implementations that always use secure
207 access to SMMU configuration registers. 207 access to SMMU configuration registers. In this case non-secure aliases of
208 secure registers have to be used during 208 secure registers have to be used during SMMU configuration.
209 209
210 stream-match-mask: 210 stream-match-mask:
211 $ref: /schemas/types.yaml#/definitions/uin 211 $ref: /schemas/types.yaml#/definitions/uint32
212 description: | 212 description: |
213 For SMMUs supporting stream matching and 213 For SMMUs supporting stream matching and using #iommu-cells = <1>,
214 specifies a mask of bits to ignore when 214 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
215 be programmed into the SMRn.MASK field o 215 be programmed into the SMRn.MASK field of every stream match register
216 used). For cases where it is desirable t 216 used). For cases where it is desirable to ignore some portion of every
217 Stream ID (e.g. for certain MMU-500 conf 217 Stream ID (e.g. for certain MMU-500 configurations given globally unique
218 input IDs). This property is not valid f 218 input IDs). This property is not valid for SMMUs using stream indexing, or
219 using stream matching with #iommu-cells 219 using stream matching with #iommu-cells = <2>, and may be ignored if
220 present in such cases. 220 present in such cases.
221 221
222 clock-names: 222 clock-names:
223 minItems: 1 223 minItems: 1
224 maxItems: 7 224 maxItems: 7
225 225
226 clocks: 226 clocks:
227 minItems: 1 227 minItems: 1
228 maxItems: 7 228 maxItems: 7
229 229
230 power-domains: 230 power-domains:
231 minItems: 1 231 minItems: 1
232 maxItems: 3 232 maxItems: 3
233 233
234 nvidia,memory-controller: 234 nvidia,memory-controller:
235 description: | 235 description: |
236 A phandle to the memory controller on NV 236 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
237 The memory controller needs to be progra 237 The memory controller needs to be programmed with a mapping of memory
238 client IDs to ARM SMMU stream IDs. 238 client IDs to ARM SMMU stream IDs.
239 239
240 If this property is absent, the mapping 240 If this property is absent, the mapping programmed by early firmware
241 will be used and it is not guaranteed th 241 will be used and it is not guaranteed that IOMMU translations will be
242 enabled for any given device. 242 enabled for any given device.
243 $ref: /schemas/types.yaml#/definitions/pha 243 $ref: /schemas/types.yaml#/definitions/phandle
244 244
245 required: 245 required:
246 - compatible 246 - compatible
247 - reg 247 - reg
248 - '#global-interrupts' 248 - '#global-interrupts'
249 - '#iommu-cells' 249 - '#iommu-cells'
250 - interrupts 250 - interrupts
251 251
252 additionalProperties: false 252 additionalProperties: false
253 253
254 allOf: 254 allOf:
255 - if: 255 - if:
256 properties: 256 properties:
257 compatible: 257 compatible:
258 contains: 258 contains:
259 enum: 259 enum:
260 - nvidia,tegra186-smmu 260 - nvidia,tegra186-smmu
261 - nvidia,tegra194-smmu 261 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu 262 - nvidia,tegra234-smmu
263 then: 263 then:
264 properties: 264 properties:
265 reg: 265 reg:
266 minItems: 1 266 minItems: 1
267 maxItems: 2 267 maxItems: 2
268 268
269 # The reference to the memory controller 269 # The reference to the memory controller is required to ensure that the
270 # memory client to stream ID mapping can 270 # memory client to stream ID mapping can be done synchronously with the
271 # IOMMU attachment. 271 # IOMMU attachment.
272 required: 272 required:
273 - nvidia,memory-controller 273 - nvidia,memory-controller
274 else: 274 else:
275 properties: 275 properties:
276 reg: 276 reg:
277 maxItems: 1 277 maxItems: 1
278 278
279 - if: 279 - if:
280 properties: 280 properties:
281 compatible: 281 compatible:
282 contains: 282 contains:
283 enum: 283 enum:
284 - qcom,msm8998-smmu-v2 284 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2 285 - qcom,sdm630-smmu-v2
286 then: 286 then:
287 anyOf: 287 anyOf:
288 - properties: 288 - properties:
289 clock-names: 289 clock-names:
290 items: 290 items:
291 - const: bus 291 - const: bus
292 clocks: 292 clocks:
293 items: 293 items:
294 - description: bus clock requi 294 - description: bus clock required for downstream bus access and for
295 the smmu ptw 295 the smmu ptw
296 - properties: 296 - properties:
297 clock-names: 297 clock-names:
298 items: 298 items:
299 - const: iface 299 - const: iface
300 - const: mem 300 - const: mem
301 - const: mem_iface 301 - const: mem_iface
302 clocks: 302 clocks:
303 items: 303 items:
304 - description: interface clock 304 - description: interface clock required to access smmu's registers
305 through the TCU's programm 305 through the TCU's programming interface.
306 - description: bus clock requi 306 - description: bus clock required for memory access
307 - description: bus clock requi 307 - description: bus clock required for GPU memory access
308 - properties: 308 - properties:
309 clock-names: 309 clock-names:
310 items: 310 items:
311 - const: iface-mm 311 - const: iface-mm
312 - const: iface-smmu 312 - const: iface-smmu
313 - const: bus-smmu 313 - const: bus-smmu
314 clocks: 314 clocks:
315 items: 315 items:
316 - description: interface clock 316 - description: interface clock required to access mnoc's registers
317 through the TCU's programm 317 through the TCU's programming interface.
318 - description: interface clock 318 - description: interface clock required to access smmu's registers
319 through the TCU's programm 319 through the TCU's programming interface.
320 - description: bus clock requi 320 - description: bus clock required for the smmu ptw
321 321
322 - if: 322 - if:
323 properties: 323 properties:
324 compatible: 324 compatible:
325 contains: 325 contains:
326 enum: 326 enum:
327 - qcom,sm6375-smmu-v2 327 - qcom,sm6375-smmu-v2
328 then: 328 then:
329 anyOf: 329 anyOf:
330 - properties: 330 - properties:
331 clock-names: 331 clock-names:
332 items: 332 items:
333 - const: bus 333 - const: bus
334 clocks: 334 clocks:
335 items: 335 items:
336 - description: bus clock requi 336 - description: bus clock required for downstream bus access and for
337 the smmu ptw 337 the smmu ptw
338 - properties: 338 - properties:
339 clock-names: 339 clock-names:
340 items: 340 items:
341 - const: iface 341 - const: iface
342 - const: mem 342 - const: mem
343 - const: mem_iface 343 - const: mem_iface
344 clocks: 344 clocks:
345 items: 345 items:
346 - description: interface clock 346 - description: interface clock required to access smmu's registers
347 through the TCU's programm 347 through the TCU's programming interface.
348 - description: bus clock requi 348 - description: bus clock required for memory access
349 - description: bus clock requi 349 - description: bus clock required for GPU memory access
350 - properties: 350 - properties:
351 clock-names: 351 clock-names:
352 items: 352 items:
353 - const: iface-mm 353 - const: iface-mm
354 - const: iface-smmu 354 - const: iface-smmu
355 - const: bus-mm 355 - const: bus-mm
356 - const: bus-smmu 356 - const: bus-smmu
357 clocks: 357 clocks:
358 items: 358 items:
359 - description: interface clock 359 - description: interface clock required to access mnoc's registers
360 through the TCU's programm 360 through the TCU's programming interface.
361 - description: interface clock 361 - description: interface clock required to access smmu's registers
362 through the TCU's programm 362 through the TCU's programming interface.
363 - description: bus clock requi 363 - description: bus clock required for downstream bus access
364 - description: bus clock requi 364 - description: bus clock required for the smmu ptw
365 365
366 - if: 366 - if:
367 properties: 367 properties:
368 compatible: 368 compatible:
369 contains: 369 contains:
370 enum: 370 enum:
371 - qcom,msm8996-smmu-v2 371 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2 372 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2 373 - qcom,sdm845-smmu-v2
374 then: 374 then:
375 properties: 375 properties:
376 clock-names: 376 clock-names:
377 items: 377 items:
378 - const: bus 378 - const: bus
379 - const: iface 379 - const: iface
380 380
381 clocks: 381 clocks:
382 items: 382 items:
383 - description: bus clock required 383 - description: bus clock required for downstream bus access and for
384 the smmu ptw 384 the smmu ptw
385 - description: interface clock req 385 - description: interface clock required to access smmu's registers
386 through the TCU's programming 386 through the TCU's programming interface.
387 387
388 - if: 388 - if:
389 properties: 389 properties:
390 compatible: 390 compatible:
391 contains: 391 contains:
392 enum: 392 enum:
393 - qcom,sa8775p-smmu-500 393 - qcom,sa8775p-smmu-500
394 - qcom,sc7280-smmu-500 394 - qcom,sc7280-smmu-500
395 - qcom,sc8280xp-smmu-500 395 - qcom,sc8280xp-smmu-500
396 then: 396 then:
397 properties: 397 properties:
398 clock-names: 398 clock-names:
399 items: 399 items:
400 - const: gcc_gpu_memnoc_gfx_clk 400 - const: gcc_gpu_memnoc_gfx_clk
401 - const: gcc_gpu_snoc_dvm_gfx_clk 401 - const: gcc_gpu_snoc_dvm_gfx_clk
402 - const: gpu_cc_ahb_clk 402 - const: gpu_cc_ahb_clk
403 - const: gpu_cc_hlos1_vote_gpu_smm 403 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
404 - const: gpu_cc_cx_gmu_clk 404 - const: gpu_cc_cx_gmu_clk
405 - const: gpu_cc_hub_cx_int_clk 405 - const: gpu_cc_hub_cx_int_clk
406 - const: gpu_cc_hub_aon_clk 406 - const: gpu_cc_hub_aon_clk
407 407
408 clocks: 408 clocks:
409 items: 409 items:
410 - description: GPU memnoc_gfx cloc 410 - description: GPU memnoc_gfx clock
411 - description: GPU snoc_dvm_gfx cl 411 - description: GPU snoc_dvm_gfx clock
412 - description: GPU ahb clock 412 - description: GPU ahb clock
413 - description: GPU hlos1_vote_GPU 413 - description: GPU hlos1_vote_GPU smmu clock
414 - description: GPU cx_gmu clock 414 - description: GPU cx_gmu clock
415 - description: GPU hub_cx_int cloc 415 - description: GPU hub_cx_int clock
416 - description: GPU hub_aon clock 416 - description: GPU hub_aon clock
417 417
418 - if: 418 - if:
419 properties: 419 properties:
420 compatible: 420 compatible:
421 contains: 421 contains:
422 enum: 422 enum:
423 - qcom,sc8180x-smmu-500 423 - qcom,sc8180x-smmu-500
424 - qcom,sm6350-smmu-v2 424 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2 425 - qcom,sm7150-smmu-v2
426 - qcom,sm8150-smmu-500 426 - qcom,sm8150-smmu-500
427 - qcom,sm8250-smmu-500 427 - qcom,sm8250-smmu-500
428 then: 428 then:
429 properties: 429 properties:
430 clock-names: 430 clock-names:
431 items: 431 items:
432 - const: ahb 432 - const: ahb
433 - const: bus 433 - const: bus
434 - const: iface 434 - const: iface
435 435
436 clocks: 436 clocks:
437 items: 437 items:
438 - description: bus clock required 438 - description: bus clock required for AHB bus access
439 - description: bus clock required 439 - description: bus clock required for downstream bus access and for
440 the smmu ptw 440 the smmu ptw
441 - description: interface clock req 441 - description: interface clock required to access smmu's registers
442 through the TCU's programming 442 through the TCU's programming interface.
443 443
444 - if: 444 - if:
445 properties: 445 properties:
446 compatible: 446 compatible:
447 items: 447 items:
448 - enum: 448 - enum:
449 - qcom,sm8350-smmu-500 449 - qcom,sm8350-smmu-500
450 - const: qcom,adreno-smmu 450 - const: qcom,adreno-smmu
451 - const: qcom,smmu-500 451 - const: qcom,smmu-500
452 - const: arm,mmu-500 452 - const: arm,mmu-500
453 then: 453 then:
454 properties: 454 properties:
455 clock-names: 455 clock-names:
456 items: 456 items:
457 - const: bus 457 - const: bus
458 - const: iface 458 - const: iface
459 - const: ahb 459 - const: ahb
460 - const: hlos1_vote_gpu_smmu 460 - const: hlos1_vote_gpu_smmu
461 - const: cx_gmu 461 - const: cx_gmu
462 - const: hub_cx_int 462 - const: hub_cx_int
463 - const: hub_aon 463 - const: hub_aon
464 clocks: 464 clocks:
465 minItems: 7 465 minItems: 7
466 maxItems: 7 466 maxItems: 7
467 467
468 - if: 468 - if:
469 properties: 469 properties:
470 compatible: 470 compatible:
471 items: 471 items:
472 - enum: 472 - enum:
473 - qcom,qcm2290-smmu-500 473 - qcom,qcm2290-smmu-500
474 - qcom,sm6115-smmu-500 474 - qcom,sm6115-smmu-500
475 - qcom,sm6125-smmu-500 475 - qcom,sm6125-smmu-500
476 - const: qcom,adreno-smmu 476 - const: qcom,adreno-smmu
477 - const: qcom,smmu-500 477 - const: qcom,smmu-500
478 - const: arm,mmu-500 478 - const: arm,mmu-500
479 then: 479 then:
480 properties: 480 properties:
481 clock-names: 481 clock-names:
482 items: 482 items:
483 - const: mem 483 - const: mem
484 - const: hlos 484 - const: hlos
485 - const: iface 485 - const: iface
486 486
487 clocks: 487 clocks:
488 items: 488 items:
489 - description: GPU memory bus cloc 489 - description: GPU memory bus clock
490 - description: Voter clock require 490 - description: Voter clock required for HLOS SMMU access
491 - description: Interface clock req 491 - description: Interface clock required for register access
492 492
493 - if: 493 - if:
494 properties: 494 properties:
495 compatible: 495 compatible:
496 items: 496 items:
497 - const: qcom,sm8450-smmu-500 497 - const: qcom,sm8450-smmu-500
498 - const: qcom,adreno-smmu 498 - const: qcom,adreno-smmu
499 - const: qcom,smmu-500 499 - const: qcom,smmu-500
500 - const: arm,mmu-500 500 - const: arm,mmu-500
501 501
502 then: 502 then:
503 properties: 503 properties:
504 clock-names: 504 clock-names:
505 items: 505 items:
506 - const: gmu 506 - const: gmu
507 - const: hub 507 - const: hub
508 - const: hlos 508 - const: hlos
509 - const: bus 509 - const: bus
510 - const: iface 510 - const: iface
511 - const: ahb 511 - const: ahb
512 512
513 clocks: 513 clocks:
514 items: 514 items:
515 - description: GMU clock 515 - description: GMU clock
516 - description: GPU HUB clock 516 - description: GPU HUB clock
517 - description: HLOS vote clock 517 - description: HLOS vote clock
518 - description: GPU memory bus cloc 518 - description: GPU memory bus clock
519 - description: GPU SNoC bus clock 519 - description: GPU SNoC bus clock
520 - description: GPU AHB clock 520 - description: GPU AHB clock
521 521
522 - if: 522 - if:
523 properties: 523 properties:
524 compatible: 524 compatible:
525 items: 525 items:
526 - enum: 526 - enum:
527 - qcom,sm8550-smmu-500 527 - qcom,sm8550-smmu-500
528 - qcom,sm8650-smmu-500 528 - qcom,sm8650-smmu-500
529 - qcom,x1e80100-smmu-500 529 - qcom,x1e80100-smmu-500
530 - const: qcom,adreno-smmu 530 - const: qcom,adreno-smmu
531 - const: qcom,smmu-500 531 - const: qcom,smmu-500
532 - const: arm,mmu-500 532 - const: arm,mmu-500
533 then: 533 then:
534 properties: 534 properties:
535 clock-names: 535 clock-names:
536 items: 536 items:
537 - const: hlos 537 - const: hlos
538 - const: bus 538 - const: bus
539 - const: iface 539 - const: iface
540 - const: ahb 540 - const: ahb
541 541
542 clocks: 542 clocks:
543 items: 543 items:
544 - description: HLOS vote clock 544 - description: HLOS vote clock
545 - description: GPU memory bus cloc 545 - description: GPU memory bus clock
546 - description: GPU SNoC bus clock 546 - description: GPU SNoC bus clock
547 - description: GPU AHB clock 547 - description: GPU AHB clock
548 548
549 # Disallow clocks for all other platforms wi 549 # Disallow clocks for all other platforms with specific compatibles
550 - if: 550 - if:
551 properties: 551 properties:
552 compatible: 552 compatible:
553 contains: 553 contains:
554 enum: 554 enum:
555 - cavium,smmu-v2 555 - cavium,smmu-v2
556 - marvell,ap806-smmu-500 556 - marvell,ap806-smmu-500
557 - nvidia,smmu-500 557 - nvidia,smmu-500
558 - qcom,qcs8300-smmu-500 558 - qcom,qcs8300-smmu-500
559 - qcom,qdu1000-smmu-500 559 - qcom,qdu1000-smmu-500
560 - qcom,sa8255p-smmu-500 560 - qcom,sa8255p-smmu-500
561 - qcom,sc7180-smmu-500 561 - qcom,sc7180-smmu-500
562 - qcom,sdm670-smmu-500 562 - qcom,sdm670-smmu-500
563 - qcom,sdm845-smmu-500 563 - qcom,sdm845-smmu-500
564 - qcom,sdx55-smmu-500 564 - qcom,sdx55-smmu-500
565 - qcom,sdx65-smmu-500 565 - qcom,sdx65-smmu-500
566 - qcom,sm6350-smmu-500 566 - qcom,sm6350-smmu-500
567 - qcom,sm6375-smmu-500 567 - qcom,sm6375-smmu-500
568 then: 568 then:
569 properties: 569 properties:
570 clock-names: false 570 clock-names: false
571 clocks: false 571 clocks: false
572 572
573 - if: 573 - if:
574 properties: 574 properties:
575 compatible: 575 compatible:
576 contains: 576 contains:
577 const: qcom,sm6375-smmu-500 577 const: qcom,sm6375-smmu-500
578 then: 578 then:
579 properties: 579 properties:
580 power-domains: 580 power-domains:
581 items: 581 items:
582 - description: SNoC MMU TBU RT GDS 582 - description: SNoC MMU TBU RT GDSC
583 - description: SNoC MMU TBU NRT GD 583 - description: SNoC MMU TBU NRT GDSC
584 - description: SNoC TURING MMU TBU 584 - description: SNoC TURING MMU TBU0 GDSC
585 585
586 required: 586 required:
587 - power-domains 587 - power-domains
588 else: 588 else:
589 properties: 589 properties:
590 power-domains: 590 power-domains:
591 maxItems: 1 591 maxItems: 1
592 592
593 examples: 593 examples:
594 - |+ 594 - |+
595 /* SMMU with stream matching or stream ind 595 /* SMMU with stream matching or stream indexing */
596 smmu1: iommu@ba5e0000 { 596 smmu1: iommu@ba5e0000 {
597 compatible = "arm,smmu-v1"; 597 compatible = "arm,smmu-v1";
598 reg = <0xba5e0000 0x10000>; 598 reg = <0xba5e0000 0x10000>;
599 #global-interrupts = <2>; 599 #global-interrupts = <2>;
600 interrupts = <0 32 4>, 600 interrupts = <0 32 4>,
601 <0 33 4>, 601 <0 33 4>,
602 <0 34 4>, /* This is 602 <0 34 4>, /* This is the first context interrupt */
603 <0 35 4>, 603 <0 35 4>,
604 <0 36 4>, 604 <0 36 4>,
605 <0 37 4>; 605 <0 37 4>;
606 #iommu-cells = <1>; 606 #iommu-cells = <1>;
607 }; 607 };
608 608
609 /* device with two stream IDs, 0 and 7 */ 609 /* device with two stream IDs, 0 and 7 */
610 master1 { 610 master1 {
611 iommus = <&smmu1 0>, 611 iommus = <&smmu1 0>,
612 <&smmu1 7>; 612 <&smmu1 7>;
613 }; 613 };
614 614
615 615
616 /* SMMU with stream matching */ 616 /* SMMU with stream matching */
617 smmu2: iommu@ba5f0000 { 617 smmu2: iommu@ba5f0000 {
618 compatible = "arm,smmu-v1"; 618 compatible = "arm,smmu-v1";
619 reg = <0xba5f0000 0x10000>; 619 reg = <0xba5f0000 0x10000>;
620 #global-interrupts = <2>; 620 #global-interrupts = <2>;
621 interrupts = <0 38 4>, 621 interrupts = <0 38 4>,
622 <0 39 4>, 622 <0 39 4>,
623 <0 40 4>, /* This is 623 <0 40 4>, /* This is the first context interrupt */
624 <0 41 4>, 624 <0 41 4>,
625 <0 42 4>, 625 <0 42 4>,
626 <0 43 4>; 626 <0 43 4>;
627 #iommu-cells = <2>; 627 #iommu-cells = <2>;
628 }; 628 };
629 629
630 /* device with stream IDs 0 and 7 */ 630 /* device with stream IDs 0 and 7 */
631 master2 { 631 master2 {
632 iommus = <&smmu2 0 0>, 632 iommus = <&smmu2 0 0>,
633 <&smmu2 7 0>; 633 <&smmu2 7 0>;
634 }; 634 };
635 635
636 /* device with stream IDs 1, 17, 33 and 49 636 /* device with stream IDs 1, 17, 33 and 49 */
637 master3 { 637 master3 {
638 iommus = <&smmu2 1 0x30>; 638 iommus = <&smmu2 1 0x30>;
639 }; 639 };
640 640
641 641
642 /* ARM MMU-500 with 10-bit stream ID input 642 /* ARM MMU-500 with 10-bit stream ID input configuration */
643 smmu3: iommu@ba600000 { 643 smmu3: iommu@ba600000 {
644 compatible = "arm,mmu-500", "arm,s 644 compatible = "arm,mmu-500", "arm,smmu-v2";
645 reg = <0xba600000 0x10000>; 645 reg = <0xba600000 0x10000>;
646 #global-interrupts = <2>; 646 #global-interrupts = <2>;
647 interrupts = <0 44 4>, 647 interrupts = <0 44 4>,
648 <0 45 4>, 648 <0 45 4>,
649 <0 46 4>, /* This is 649 <0 46 4>, /* This is the first context interrupt */
650 <0 47 4>, 650 <0 47 4>,
651 <0 48 4>, 651 <0 48 4>,
652 <0 49 4>; 652 <0 49 4>;
653 #iommu-cells = <1>; 653 #iommu-cells = <1>;
654 /* always ignore appended 5-bit TB 654 /* always ignore appended 5-bit TBU number */
655 stream-match-mask = <0x7c00>; 655 stream-match-mask = <0x7c00>;
656 }; 656 };
657 657
658 bus { 658 bus {
659 /* bus whose child devices emit on 659 /* bus whose child devices emit one unique 10-bit stream
660 ID each, but may master through 660 ID each, but may master through multiple SMMU TBUs */
661 iommu-map = <0 &smmu3 0 0x400>; 661 iommu-map = <0 &smmu3 0 0x400>;
662 662
663 663
664 }; 664 };
665 665
666 - |+ 666 - |+
667 /* Qcom's arm,smmu-v2 implementation */ 667 /* Qcom's arm,smmu-v2 implementation */
668 #include <dt-bindings/interrupt-controller 668 #include <dt-bindings/interrupt-controller/arm-gic.h>
669 #include <dt-bindings/interrupt-controller 669 #include <dt-bindings/interrupt-controller/irq.h>
670 smmu4: iommu@d00000 { 670 smmu4: iommu@d00000 {
671 compatible = "qcom,msm8996-smmu-v2", "qc 671 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
672 reg = <0xd00000 0x10000>; 672 reg = <0xd00000 0x10000>;
673 673
674 #global-interrupts = <1>; 674 #global-interrupts = <1>;
675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_ 675 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH> 676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH> 677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
678 #iommu-cells = <1>; 678 #iommu-cells = <1>;
679 power-domains = <&mmcc 0>; 679 power-domains = <&mmcc 0>;
680 680
681 clocks = <&mmcc 123>, 681 clocks = <&mmcc 123>,
682 <&mmcc 124>; 682 <&mmcc 124>;
683 clock-names = "bus", "iface"; 683 clock-names = "bus", "iface";
684 }; 684 };
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