1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/qcom, 4 $id: http://devicetree.org/schemas/iommu/qcom,tbu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm TBU (Translation Buffer Unit) 7 title: Qualcomm TBU (Translation Buffer Unit)
8 8
9 maintainers: 9 maintainers:
10 - Georgi Djakov <quic_c_gdjako@quicinc.com> 10 - Georgi Djakov <quic_c_gdjako@quicinc.com>
11 11
12 description: 12 description:
13 The Qualcomm SMMU500 implementation consists 13 The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains
14 a Translation Lookaside Buffer (TLB) that ca 14 a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides
15 debug features to trace and trigger debug tr 15 debug features to trace and trigger debug transactions. There are multiple TBU
16 instances with each client core. 16 instances with each client core.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 enum: 20 enum:
21 - qcom,sc7280-tbu 21 - qcom,sc7280-tbu
22 - qcom,sdm845-tbu 22 - qcom,sdm845-tbu
23 23
24 reg: 24 reg:
25 maxItems: 1 25 maxItems: 1
26 26
27 clocks: 27 clocks:
28 maxItems: 1 28 maxItems: 1
29 29
30 interconnects: 30 interconnects:
31 maxItems: 1 31 maxItems: 1
32 32
33 power-domains: 33 power-domains:
34 maxItems: 1 34 maxItems: 1
35 35
36 qcom,stream-id-range: 36 qcom,stream-id-range:
37 description: | 37 description: |
38 Phandle of a SMMU device and Stream ID r 38 Phandle of a SMMU device and Stream ID range (address and size) that
39 is assigned by the TBU 39 is assigned by the TBU
40 $ref: /schemas/types.yaml#/definitions/pha 40 $ref: /schemas/types.yaml#/definitions/phandle-array
41 items: 41 items:
42 - items: 42 - items:
43 - description: phandle of a smmu nod 43 - description: phandle of a smmu node
44 - description: stream id base addres 44 - description: stream id base address
45 - description: stream id size 45 - description: stream id size
46 46
47 required: 47 required:
48 - compatible 48 - compatible
49 - reg 49 - reg
50 - qcom,stream-id-range 50 - qcom,stream-id-range
51 51
52 additionalProperties: false 52 additionalProperties: false
53 53
54 examples: 54 examples:
55 - | 55 - |
56 #include <dt-bindings/clock/qcom,gcc-sdm84 56 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
57 #include <dt-bindings/interconnect/qcom,ic 57 #include <dt-bindings/interconnect/qcom,icc.h>
58 #include <dt-bindings/interconnect/qcom,sd 58 #include <dt-bindings/interconnect/qcom,sdm845.h>
59 59
60 tbu@150e1000 { 60 tbu@150e1000 {
61 compatible = "qcom,sdm845-tbu"; 61 compatible = "qcom,sdm845-tbu";
62 reg = <0x150e1000 0x1000>; 62 reg = <0x150e1000 0x1000>;
63 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_ 63 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
64 interconnects = <&system_noc MASTER_GN 64 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
65 &config_noc SLAVE_IME 65 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
66 power-domains = <&gcc HLOS1_VOTE_AGGRE 66 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
67 qcom,stream-id-range = <&apps_smmu 0x1 67 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
68 }; 68 };
69 ... 69 ...
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