1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/rockc 4 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip IOMMU 7 title: Rockchip IOMMU
8 8
9 maintainers: 9 maintainers:
10 - Heiko Stuebner <heiko@sntech.de> 10 - Heiko Stuebner <heiko@sntech.de>
11 11
12 description: |+ 12 description: |+
13 A Rockchip DRM iommu translates io virtual a 13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
14 its master device. Each slave device is boun 14 its master device. Each slave device is bound to a single master device and
15 shares its clocks, power domain and irq. 15 shares its clocks, power domain and irq.
16 16
17 For information on assigning IOMMU controlle 17 For information on assigning IOMMU controller to its peripheral devices,
18 see generic IOMMU bindings. 18 see generic IOMMU bindings.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 oneOf: !! 22 enum:
23 - enum: !! 23 - rockchip,iommu
24 - rockchip,iommu !! 24 - rockchip,rk3568-iommu
25 - rockchip,rk3568-iommu <<
26 - items: <<
27 - enum: <<
28 - rockchip,rk3588-iommu <<
29 - const: rockchip,rk3568-iommu <<
30 25
31 reg: 26 reg:
32 items: 27 items:
33 - description: configuration registers f 28 - description: configuration registers for MMU instance 0
34 - description: configuration registers f 29 - description: configuration registers for MMU instance 1
35 minItems: 1 30 minItems: 1
36 31
37 interrupts: 32 interrupts:
38 items: 33 items:
39 - description: interruption for MMU inst 34 - description: interruption for MMU instance 0
40 - description: interruption for MMU inst 35 - description: interruption for MMU instance 1
41 minItems: 1 36 minItems: 1
42 37
43 clocks: 38 clocks:
44 items: 39 items:
45 - description: Core clock 40 - description: Core clock
46 - description: Interface clock 41 - description: Interface clock
47 42
48 clock-names: 43 clock-names:
49 items: 44 items:
50 - const: aclk 45 - const: aclk
51 - const: iface 46 - const: iface
52 47
53 "#iommu-cells": 48 "#iommu-cells":
54 const: 0 49 const: 0
55 50
56 power-domains: 51 power-domains:
57 maxItems: 1 52 maxItems: 1
58 53
59 rockchip,disable-mmu-reset: 54 rockchip,disable-mmu-reset:
60 $ref: /schemas/types.yaml#/definitions/fla 55 $ref: /schemas/types.yaml#/definitions/flag
61 description: | 56 description: |
62 Do not use the mmu reset operation. 57 Do not use the mmu reset operation.
63 Some mmu instances may produce unexpecte 58 Some mmu instances may produce unexpected results
64 when the reset operation is used. 59 when the reset operation is used.
65 60
66 required: 61 required:
67 - compatible 62 - compatible
68 - reg 63 - reg
69 - interrupts 64 - interrupts
70 - clocks 65 - clocks
71 - clock-names 66 - clock-names
72 - "#iommu-cells" 67 - "#iommu-cells"
73 68
74 additionalProperties: false 69 additionalProperties: false
75 70
76 examples: 71 examples:
77 - | 72 - |
78 #include <dt-bindings/clock/rk3399-cru.h> 73 #include <dt-bindings/clock/rk3399-cru.h>
79 #include <dt-bindings/interrupt-controller 74 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 75
81 vopl_mmu: iommu@ff940300 { 76 vopl_mmu: iommu@ff940300 {
82 compatible = "rockchip,iommu"; 77 compatible = "rockchip,iommu";
83 reg = <0xff940300 0x100>; 78 reg = <0xff940300 0x100>;
84 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_ 79 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VO 80 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
86 clock-names = "aclk", "iface"; 81 clock-names = "aclk", "iface";
87 #iommu-cells = <0>; 82 #iommu-cells = <0>;
88 }; 83 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.