1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iommu/rockc 4 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip IOMMU 7 title: Rockchip IOMMU
8 8
9 maintainers: 9 maintainers:
10 - Heiko Stuebner <heiko@sntech.de> 10 - Heiko Stuebner <heiko@sntech.de>
11 11
12 description: |+ 12 description: |+
13 A Rockchip DRM iommu translates io virtual a 13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
14 its master device. Each slave device is boun 14 its master device. Each slave device is bound to a single master device and
15 shares its clocks, power domain and irq. 15 shares its clocks, power domain and irq.
16 16
17 For information on assigning IOMMU controlle 17 For information on assigning IOMMU controller to its peripheral devices,
18 see generic IOMMU bindings. 18 see generic IOMMU bindings.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 oneOf: 22 oneOf:
23 - enum: 23 - enum:
24 - rockchip,iommu 24 - rockchip,iommu
25 - rockchip,rk3568-iommu 25 - rockchip,rk3568-iommu
26 - items: 26 - items:
27 - enum: 27 - enum:
28 - rockchip,rk3588-iommu 28 - rockchip,rk3588-iommu
29 - const: rockchip,rk3568-iommu 29 - const: rockchip,rk3568-iommu
30 30
31 reg: 31 reg:
32 items: 32 items:
33 - description: configuration registers f 33 - description: configuration registers for MMU instance 0
34 - description: configuration registers f 34 - description: configuration registers for MMU instance 1
35 minItems: 1 35 minItems: 1
36 36
37 interrupts: 37 interrupts:
38 items: 38 items:
39 - description: interruption for MMU inst 39 - description: interruption for MMU instance 0
40 - description: interruption for MMU inst 40 - description: interruption for MMU instance 1
41 minItems: 1 41 minItems: 1
42 42
43 clocks: 43 clocks:
44 items: 44 items:
45 - description: Core clock 45 - description: Core clock
46 - description: Interface clock 46 - description: Interface clock
47 47
48 clock-names: 48 clock-names:
49 items: 49 items:
50 - const: aclk 50 - const: aclk
51 - const: iface 51 - const: iface
52 52
53 "#iommu-cells": 53 "#iommu-cells":
54 const: 0 54 const: 0
55 55
56 power-domains: 56 power-domains:
57 maxItems: 1 57 maxItems: 1
58 58
59 rockchip,disable-mmu-reset: 59 rockchip,disable-mmu-reset:
60 $ref: /schemas/types.yaml#/definitions/fla 60 $ref: /schemas/types.yaml#/definitions/flag
61 description: | 61 description: |
62 Do not use the mmu reset operation. 62 Do not use the mmu reset operation.
63 Some mmu instances may produce unexpecte 63 Some mmu instances may produce unexpected results
64 when the reset operation is used. 64 when the reset operation is used.
65 65
66 required: 66 required:
67 - compatible 67 - compatible
68 - reg 68 - reg
69 - interrupts 69 - interrupts
70 - clocks 70 - clocks
71 - clock-names 71 - clock-names
72 - "#iommu-cells" 72 - "#iommu-cells"
73 73
74 additionalProperties: false 74 additionalProperties: false
75 75
76 examples: 76 examples:
77 - | 77 - |
78 #include <dt-bindings/clock/rk3399-cru.h> 78 #include <dt-bindings/clock/rk3399-cru.h>
79 #include <dt-bindings/interrupt-controller 79 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 80
81 vopl_mmu: iommu@ff940300 { 81 vopl_mmu: iommu@ff940300 {
82 compatible = "rockchip,iommu"; 82 compatible = "rockchip,iommu";
83 reg = <0xff940300 0x100>; 83 reg = <0xff940300 0x100>;
84 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_ 84 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VO 85 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
86 clock-names = "aclk", "iface"; 86 clock-names = "aclk", "iface";
87 #iommu-cells = <0>; 87 #iommu-cells = <0>;
88 }; 88 };
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