1 Broadcom FlexRM Ring Manager
2 ============================
3 The Broadcom FlexRM ring manager provides a se
4 used to submit work to offload engines. An SoC
5 hardware blocks. There is one device tree entr
6 FlexRM driver will create a mailbox-controller
7 hardware block where each mailbox channel is a
8
9 Required properties:
10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-m
12 - reg: Specifies base physical addres
13 ring registers
14 - msi-parent: Phandles (and potential Device
15 The FlexRM engine will send MS
16 interrupts) to CPU. There is o
17 Refer devicetree/bindings/inte
18 - #mbox-cells: Specifies the number of cells
19 channel. This should be 3.
20
21 The 1st cell is the mailbox ch
22
23 The 2nd cell contains MSI comp
24 number of completion messages
25 one MSI interrupt to CPU.
26
27 The 3rd cell contains MSI time
28 which FlexRM will wait to accu
29 where N is the value specified
30 does not get required number o
31 specified by this cell then it
32 to CPU provided at least one c
33
34 Optional properties:
35 --------------------
36 - dma-coherent: Present if DMA operations made
37 as DMA descriptor access, acce
38 descriptors and read/write poi
39 cache coherent with the CPU.
40
41 Example:
42 --------
43 crypto_mbox: mbox@67000000 {
44 compatible = "brcm,iproc-flexrm-mbox";
45 reg = <0x67000000 0x200000>;
46 msi-parent = <&gic_its 0x7f00>;
47 #mbox-cells = <3>;
48 };
49
50 crypto@672c0000 {
51 compatible = "brcm,spu2-v2-crypto";
52 reg = <0x672c0000 0x1000>;
53 mboxes = <&crypto_mbox 0 0x1 0xffff>,
54 <&crypto_mbox 1 0x1 0xffff>,
55 <&crypto_mbox 16 0x1 0xffff>,
56 <&crypto_mbox 17 0x1 0xffff>,
57 <&crypto_mbox 30 0x1 0xffff>,
58 <&crypto_mbox 31 0x1 0xffff>;
59 };
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