1 Broadcom FlexRM Ring Manager 1 Broadcom FlexRM Ring Manager
2 ============================ 2 ============================
3 The Broadcom FlexRM ring manager provides a se 3 The Broadcom FlexRM ring manager provides a set of rings which can be
4 used to submit work to offload engines. An SoC 4 used to submit work to offload engines. An SoC may have multiple FlexRM
5 hardware blocks. There is one device tree entr 5 hardware blocks. There is one device tree entry per FlexRM block. The
6 FlexRM driver will create a mailbox-controller 6 FlexRM driver will create a mailbox-controller instance for given FlexRM
7 hardware block where each mailbox channel is a 7 hardware block where each mailbox channel is a separate FlexRM ring.
8 8
9 Required properties: 9 Required properties:
10 -------------------- 10 --------------------
11 - compatible: Should be "brcm,iproc-flexrm-m 11 - compatible: Should be "brcm,iproc-flexrm-mbox"
12 - reg: Specifies base physical addres 12 - reg: Specifies base physical address and size of the FlexRM
13 ring registers 13 ring registers
14 - msi-parent: Phandles (and potential Device 14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
15 The FlexRM engine will send MS 15 The FlexRM engine will send MSIs (instead of wired
16 interrupts) to CPU. There is o 16 interrupts) to CPU. There is one MSI for each FlexRM ring.
17 Refer devicetree/bindings/inte 17 Refer devicetree/bindings/interrupt-controller/msi.txt
18 - #mbox-cells: Specifies the number of cells 18 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
19 channel. This should be 3. 19 channel. This should be 3.
20 20
21 The 1st cell is the mailbox ch 21 The 1st cell is the mailbox channel number.
22 22
23 The 2nd cell contains MSI comp 23 The 2nd cell contains MSI completion threshold. This is the
24 number of completion messages 24 number of completion messages for which FlexRM will inject
25 one MSI interrupt to CPU. 25 one MSI interrupt to CPU.
26 26
27 The 3rd cell contains MSI time !! 27 The 3nd cell contains MSI timer value representing time for
28 which FlexRM will wait to accu 28 which FlexRM will wait to accumulate N completion messages
29 where N is the value specified 29 where N is the value specified by 2nd cell above. If FlexRM
30 does not get required number o 30 does not get required number of completion messages in time
31 specified by this cell then it 31 specified by this cell then it will inject one MSI interrupt
32 to CPU provided at least one c !! 32 to CPU provided atleast one completion message is available.
33 33
34 Optional properties: 34 Optional properties:
35 -------------------- 35 --------------------
36 - dma-coherent: Present if DMA operations made 36 - dma-coherent: Present if DMA operations made by the FlexRM engine (such
37 as DMA descriptor access, acce 37 as DMA descriptor access, access to buffers pointed by DMA
38 descriptors and read/write poi 38 descriptors and read/write pointer updates to DDR) are
39 cache coherent with the CPU. 39 cache coherent with the CPU.
40 40
41 Example: 41 Example:
42 -------- 42 --------
43 crypto_mbox: mbox@67000000 { 43 crypto_mbox: mbox@67000000 {
44 compatible = "brcm,iproc-flexrm-mbox"; 44 compatible = "brcm,iproc-flexrm-mbox";
45 reg = <0x67000000 0x200000>; 45 reg = <0x67000000 0x200000>;
46 msi-parent = <&gic_its 0x7f00>; 46 msi-parent = <&gic_its 0x7f00>;
47 #mbox-cells = <3>; 47 #mbox-cells = <3>;
48 }; 48 };
49 49
50 crypto@672c0000 { 50 crypto@672c0000 {
51 compatible = "brcm,spu2-v2-crypto"; 51 compatible = "brcm,spu2-v2-crypto";
52 reg = <0x672c0000 0x1000>; 52 reg = <0x672c0000 0x1000>;
53 mboxes = <&crypto_mbox 0 0x1 0xffff>, 53 mboxes = <&crypto_mbox 0 0x1 0xffff>,
54 <&crypto_mbox 1 0x1 0xffff>, 54 <&crypto_mbox 1 0x1 0xffff>,
55 <&crypto_mbox 16 0x1 0xffff>, 55 <&crypto_mbox 16 0x1 0xffff>,
56 <&crypto_mbox 17 0x1 0xffff>, 56 <&crypto_mbox 17 0x1 0xffff>,
57 <&crypto_mbox 30 0x1 0xffff>, 57 <&crypto_mbox 30 0x1 0xffff>,
58 <&crypto_mbox 31 0x1 0xffff>; 58 <&crypto_mbox 31 0x1 0xffff>;
59 }; 59 };
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