1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/media/allwi 4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Allwinner H3 Deinterlace !! 7 title: Allwinner H3 Deinterlace Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Jernej Skrabec <jernej.skrabec@siol.net> 10 - Jernej Skrabec <jernej.skrabec@siol.net>
11 - Chen-Yu Tsai <wens@csie.org> 11 - Chen-Yu Tsai <wens@csie.org>
12 - Maxime Ripard <mripard@kernel.org> 12 - Maxime Ripard <mripard@kernel.org>
13 13
14 description: |- 14 description: |-
15 The Allwinner H3 and later has a deinterlace 15 The Allwinner H3 and later has a deinterlace core used for
16 deinterlacing interlaced video content. 16 deinterlacing interlaced video content.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - const: allwinner,sun8i-h3-deinterlace 21 - const: allwinner,sun8i-h3-deinterlace
22 - items: <<
23 - const: allwinner,sun8i-r40-deinter <<
24 - const: allwinner,sun8i-h3-deinterl <<
25 - items: 22 - items:
26 - const: allwinner,sun50i-a64-deinte 23 - const: allwinner,sun50i-a64-deinterlace
27 - const: allwinner,sun8i-h3-deinterl 24 - const: allwinner,sun8i-h3-deinterlace
28 25
29 reg: 26 reg:
30 maxItems: 1 27 maxItems: 1
31 28
32 interrupts: 29 interrupts:
33 maxItems: 1 30 maxItems: 1
34 31
35 clocks: 32 clocks:
36 items: 33 items:
37 - description: Deinterlace interface clo 34 - description: Deinterlace interface clock
38 - description: Deinterlace module clock 35 - description: Deinterlace module clock
39 - description: Deinterlace DRAM clock 36 - description: Deinterlace DRAM clock
40 37
41 clock-names: 38 clock-names:
42 items: 39 items:
43 - const: bus 40 - const: bus
44 - const: mod 41 - const: mod
45 - const: ram 42 - const: ram
46 43
47 resets: 44 resets:
48 maxItems: 1 45 maxItems: 1
49 46
50 interconnects: 47 interconnects:
51 maxItems: 1 48 maxItems: 1
52 49
53 interconnect-names: 50 interconnect-names:
54 const: dma-mem 51 const: dma-mem
55 52
56 required: 53 required:
57 - compatible 54 - compatible
58 - reg 55 - reg
59 - interrupts 56 - interrupts
60 - clocks 57 - clocks
61 58
62 additionalProperties: false 59 additionalProperties: false
63 60
64 examples: 61 examples:
65 - | 62 - |
66 #include <dt-bindings/interrupt-controller 63 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 #include <dt-bindings/clock/sun8i-h3-ccu.h 64 #include <dt-bindings/clock/sun8i-h3-ccu.h>
68 #include <dt-bindings/reset/sun8i-h3-ccu.h 65 #include <dt-bindings/reset/sun8i-h3-ccu.h>
69 66
70 deinterlace: deinterlace@1400000 { 67 deinterlace: deinterlace@1400000 {
71 compatible = "allwinner,sun8i-h3-deint 68 compatible = "allwinner,sun8i-h3-deinterlace";
72 reg = <0x01400000 0x20000>; 69 reg = <0x01400000 0x20000>;
73 clocks = <&ccu CLK_BUS_DEINTERLACE>, 70 clocks = <&ccu CLK_BUS_DEINTERLACE>,
74 <&ccu CLK_DEINTERLACE>, 71 <&ccu CLK_DEINTERLACE>,
75 <&ccu CLK_DRAM_DEINTERLACE>; 72 <&ccu CLK_DRAM_DEINTERLACE>;
76 clock-names = "bus", "mod", "ram"; 73 clock-names = "bus", "mod", "ram";
77 resets = <&ccu RST_BUS_DEINTERLACE>; 74 resets = <&ccu RST_BUS_DEINTERLACE>;
78 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVE 75 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
79 interconnects = <&mbus 9>; 76 interconnects = <&mbus 9>;
80 interconnect-names = "dma-mem"; 77 interconnect-names = "dma-mem";
81 }; 78 };
82 79
83 ... 80 ...
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