1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/media/allwi 4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Allwinner H3 Deinterlace !! 7 title: Allwinner H3 Deinterlace Device Tree Bindings
8 8
9 maintainers: 9 maintainers:
10 - Jernej Skrabec <jernej.skrabec@siol.net> 10 - Jernej Skrabec <jernej.skrabec@siol.net>
11 - Chen-Yu Tsai <wens@csie.org> 11 - Chen-Yu Tsai <wens@csie.org>
12 - Maxime Ripard <mripard@kernel.org> 12 - Maxime Ripard <mripard@kernel.org>
13 13
14 description: |- 14 description: |-
15 The Allwinner H3 and later has a deinterlace 15 The Allwinner H3 and later has a deinterlace core used for
16 deinterlacing interlaced video content. 16 deinterlacing interlaced video content.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: !! 20 const: allwinner,sun8i-h3-deinterlace
21 - const: allwinner,sun8i-h3-deinterlace <<
22 - items: <<
23 - const: allwinner,sun8i-r40-deinter <<
24 - const: allwinner,sun8i-h3-deinterl <<
25 - items: <<
26 - const: allwinner,sun50i-a64-deinte <<
27 - const: allwinner,sun8i-h3-deinterl <<
28 21
29 reg: 22 reg:
30 maxItems: 1 23 maxItems: 1
31 24
32 interrupts: 25 interrupts:
33 maxItems: 1 26 maxItems: 1
34 27
35 clocks: 28 clocks:
36 items: 29 items:
37 - description: Deinterlace interface clo 30 - description: Deinterlace interface clock
38 - description: Deinterlace module clock 31 - description: Deinterlace module clock
39 - description: Deinterlace DRAM clock 32 - description: Deinterlace DRAM clock
40 33
41 clock-names: 34 clock-names:
42 items: 35 items:
43 - const: bus 36 - const: bus
44 - const: mod 37 - const: mod
45 - const: ram 38 - const: ram
46 39
47 resets: 40 resets:
48 maxItems: 1 41 maxItems: 1
49 42
50 interconnects: 43 interconnects:
51 maxItems: 1 44 maxItems: 1
52 45
53 interconnect-names: 46 interconnect-names:
54 const: dma-mem 47 const: dma-mem
55 48
56 required: 49 required:
57 - compatible 50 - compatible
58 - reg 51 - reg
59 - interrupts 52 - interrupts
60 - clocks 53 - clocks
61 54
62 additionalProperties: false 55 additionalProperties: false
63 56
64 examples: 57 examples:
65 - | 58 - |
66 #include <dt-bindings/interrupt-controller 59 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 #include <dt-bindings/clock/sun8i-h3-ccu.h 60 #include <dt-bindings/clock/sun8i-h3-ccu.h>
68 #include <dt-bindings/reset/sun8i-h3-ccu.h 61 #include <dt-bindings/reset/sun8i-h3-ccu.h>
69 62
70 deinterlace: deinterlace@1400000 { 63 deinterlace: deinterlace@1400000 {
71 compatible = "allwinner,sun8i-h3-deint 64 compatible = "allwinner,sun8i-h3-deinterlace";
72 reg = <0x01400000 0x20000>; 65 reg = <0x01400000 0x20000>;
73 clocks = <&ccu CLK_BUS_DEINTERLACE>, 66 clocks = <&ccu CLK_BUS_DEINTERLACE>,
74 <&ccu CLK_DEINTERLACE>, 67 <&ccu CLK_DEINTERLACE>,
75 <&ccu CLK_DRAM_DEINTERLACE>; 68 <&ccu CLK_DRAM_DEINTERLACE>;
76 clock-names = "bus", "mod", "ram"; 69 clock-names = "bus", "mod", "ram";
77 resets = <&ccu RST_BUS_DEINTERLACE>; 70 resets = <&ccu RST_BUS_DEINTERLACE>;
78 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVE 71 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
79 interconnects = <&mbus 9>; 72 interconnects = <&mbus 9>;
80 interconnect-names = "dma-mem"; 73 interconnect-names = "dma-mem";
81 }; 74 };
82 75
83 ... 76 ...
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