1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C
2
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/media/amphi
6 $schema: http://devicetree.org/meta-schemas/co
7
8 title: Amphion VPU codec IP
9
10 maintainers:
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
13
14 description: |-
15 The Amphion MXC video encoder(Windsor) and d
16 on NXP i.MX8Q SoCs.
17
18 properties:
19 $nodename:
20 pattern: "^vpu@[0-9a-f]+$"
21
22 compatible:
23 items:
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
27
28 reg:
29 maxItems: 1
30
31 power-domains:
32 maxItems: 1
33
34 "#address-cells":
35 const: 1
36
37 "#size-cells":
38 const: 1
39
40 ranges: true
41
42 patternProperties:
43 "^mailbox@[0-9a-f]+$":
44 description:
45 Each vpu encoder or decoder correspond a
46 between driver and firmware. Implement v
47 $ref: /schemas/mailbox/fsl,mu.yaml#
48
49
50 "^vpu-core@[0-9a-f]+$":
51 description:
52 Each core correspond a decoder or encode
53 separately. NXP i.MX8QM SoC has one deco
54 has one decoder and one encoder.
55 type: object
56
57 properties:
58 compatible:
59 items:
60 - enum:
61 - nxp,imx8q-vpu-decoder
62 - nxp,imx8q-vpu-encoder
63
64 reg:
65 maxItems: 1
66
67 power-domains:
68 maxItems: 1
69
70 mbox-names:
71 items:
72 - const: tx0
73 - const: tx1
74 - const: rx
75
76 mboxes:
77 description:
78 List of phandle of 2 MU channels for
79 maxItems: 3
80
81 memory-region:
82 description:
83 Phandle to the reserved memory nodes
84 remoteproc device. The reserved memo
85 and should be defined as per the bin
86 Documentation/devicetree/bindings/re
87 items:
88 - description: region reserved for f
89 - description: region used for RPC s
90 driver.
91
92 required:
93 - compatible
94 - reg
95 - power-domains
96 - mbox-names
97 - mboxes
98 - memory-region
99
100 additionalProperties: false
101
102 required:
103 - compatible
104 - reg
105 - power-domains
106
107 additionalProperties: false
108
109 examples:
110 # Device node example for i.MX8QM platform:
111 - |
112 #include <dt-bindings/firmware/imx/rsrc.h>
113
114 vpu: vpu@2c000000 {
115 compatible = "nxp,imx8qm-vpu";
116 ranges = <0x2c000000 0x2c000000 0x200000
117 reg = <0x2c000000 0x1000000>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 power-domains = <&pd IMX_SC_R_VPU>;
121
122 mu_m0: mailbox@2d000000 {
123 compatible = "fsl,imx6sx-mu";
124 reg = <0x2d000000 0x20000>;
125 interrupts = <0 472 4>;
126 #mbox-cells = <2>;
127 power-domains = <&pd IMX_SC_R_VPU_MU_0
128 };
129
130 mu1_m0: mailbox@2d020000 {
131 compatible = "fsl,imx6sx-mu";
132 reg = <0x2d020000 0x20000>;
133 interrupts = <0 473 4>;
134 #mbox-cells = <2>;
135 power-domains = <&pd IMX_SC_R_VPU_MU_1
136 };
137
138 mu2_m0: mailbox@2d040000 {
139 compatible = "fsl,imx6sx-mu";
140 reg = <0x2d040000 0x20000>;
141 interrupts = <0 474 4>;
142 #mbox-cells = <2>;
143 power-domains = <&pd IMX_SC_R_VPU_MU_2
144 };
145
146 vpu_core0: vpu-core@2d080000 {
147 compatible = "nxp,imx8q-vpu-decoder";
148 reg = <0x2d080000 0x10000>;
149 power-domains = <&pd IMX_SC_R_VPU_DEC_
150 mbox-names = "tx0", "tx1", "rx";
151 mboxes = <&mu_m0 0 0>,
152 <&mu_m0 0 1>,
153 <&mu_m0 1 0>;
154 memory-region = <&decoder_boot>, <&dec
155 };
156
157 vpu_core1: vpu-core@2d090000 {
158 compatible = "nxp,imx8q-vpu-encoder";
159 reg = <0x2d090000 0x10000>;
160 power-domains = <&pd IMX_SC_R_VPU_ENC_
161 mbox-names = "tx0", "tx1", "rx";
162 mboxes = <&mu1_m0 0 0>,
163 <&mu1_m0 0 1>,
164 <&mu1_m0 1 0>;
165 memory-region = <&encoder1_boot>, <&en
166 };
167
168 vpu_core2: vpu-core@2d0a0000 {
169 reg = <0x2d0a0000 0x10000>;
170 compatible = "nxp,imx8q-vpu-encoder";
171 power-domains = <&pd IMX_SC_R_VPU_ENC_
172 mbox-names = "tx0", "tx1", "rx";
173 mboxes = <&mu2_m0 0 0>,
174 <&mu2_m0 0 1>,
175 <&mu2_m0 1 0>;
176 memory-region = <&encoder2_boot>, <&en
177 };
178 };
179
180 ...
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