1 Device-Tree bindings for the NXP TDA1997x HDMI
2
3 The TDA19971/73 are HDMI video receivers.
4
5 The TDA19971 Video port output pins can be use
6 - RGB 8bit per color (24 bits total): R[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11
8 - YUV422 semi-planar 8bit per component (16 b
9 - YUV422 semi-planar 10bit per component (20
10 - YUV422 semi-planar 12bit per component (24
11 - YUV422 BT656 8bit per component (8 bits tot
12 - YUV422 BT656 10bit per component (10 bits t
13 - YUV422 BT656 12bit per component (12 bits t
14
15 The TDA19973 Video port output pins can be use
16 - RGB 12bit per color (36 bits total): R[11:0
17 - YUV444 12bit per color (36 bits total): Y[1
18 - YUV422 semi-planar 12bit per component (24
19 - YUV422 BT656 12bit per component (12 bits t
20
21 The Video port output pins are mapped via 4-bi
22 for a variety of connection possibilities incl
23 pin groups. The video_portcfg device-tree prop
24 pairs which map a chip-specific VP output regi
25 the pin group needs to be bit-swapped you can
26
27 Required Properties:
28 - compatible :
29 - "nxp,tda19971" for the TDA19971
30 - "nxp,tda19973" for the TDA19973
31 - reg : I2C slave address
32 - interrupts : The interrupt number
33 - DOVDD-supply : Digital I/O supply
34 - DVDD-supply : Digital Core supply
35 - AVDD-supply : Analog supply
36 - nxp,vidout-portcfg : array of pairs mappin
37
38 Optional Properties:
39 - nxp,audout-format : DAI bus format: "i2s"
40 - nxp,audout-width : width of audio output
41 - nxp,audout-layout : data layout (0=AP0 us
42 - nxp,audout-mclk-fs : Multiplication factor
43 mclk.
44
45 The port node shall contain one endpoint child
46 output video port, in accordance with the vide
47 Documentation/devicetree/bindings/media/video-
48
49 Optional Endpoint Properties:
50 The following three properties are defined i
51 are valid for the output parallel bus endpoi
52 - hsync-active: Horizontal synchronization p
53 - vsync-active: Vertical synchronization pol
54 - data-active: Data polarity. Defaults to ac
55
56 Examples:
57 - VP[15:0] connected to IMX6 CSI_DATA[19:4] f
58 16bit I2S layout0 with a 128*fs clock (A_WS
59 hdmi-receiver@48 {
60 compatible = "nxp,tda19971";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_tda1997x
63 reg = <0x48>;
64 interrupt-parent = <&gpio1>;
65 interrupts = <7 IRQ_TYPE_LEVEL
66 DOVDD-supply = <®_3p3v>;
67 AVDD-supply = <®_1p8v>;
68 DVDD-supply = <®_1p8v>;
69 /* audio */
70 #sound-dai-cells = <0>;
71 nxp,audout-format = "i2s";
72 nxp,audout-layout = <0>;
73 nxp,audout-width = <16>;
74 nxp,audout-mclk-fs = <128>;
75 /*
76 * The 8bpp YUV422 semi-planar
77 * and Y[11:4] across 16bits i
78 */
79 nxp,vidout-portcfg =
80 /* Y[11:8]<->VP[15:12]
81 < TDA1997X_VP24_V15_12
82 /* Y[7:4]<->VP[11:08]<
83 < TDA1997X_VP24_V11_08
84 /* CbCc[11:8]<->VP[07:
85 < TDA1997X_VP24_V07_04
86 /* CbCr[7:4]<->VP[03:0
87 < TDA1997X_VP24_V03_00
88
89 port {
90 tda1997x_to_ipu1_csi0_
91 remote-endpoin
92 bus-width = <1
93 hsync-active =
94 vsync-active =
95 data-active =
96 };
97 };
98 };
99 - VP[15:8] connected to IMX6 CSI_DATA[19:12]
100 16bit I2S layout0 with a 128*fs clock (A_WS
101 hdmi-receiver@48 {
102 compatible = "nxp,tda19971";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_tda1997x
105 reg = <0x48>;
106 interrupt-parent = <&gpio1>;
107 interrupts = <7 IRQ_TYPE_LEVEL
108 DOVDD-supply = <®_3p3v>;
109 AVDD-supply = <®_1p8v>;
110 DVDD-supply = <®_1p8v>;
111 /* audio */
112 #sound-dai-cells = <0>;
113 nxp,audout-format = "i2s";
114 nxp,audout-layout = <0>;
115 nxp,audout-width = <16>;
116 nxp,audout-mclk-fs = <128>;
117 /*
118 * The 8bpp YUV422 semi-planar
119 * and Y[11:4] across 16bits i
120 */
121 nxp,vidout-portcfg =
122 /* Y[11:8]<->VP[15:12]
123 < TDA1997X_VP24_V15_12
124 /* Y[7:4]<->VP[11:08]<
125 < TDA1997X_VP24_V11_08
126 /* CbCc[11:8]<->VP[07:
127 < TDA1997X_VP24_V07_04
128 /* CbCr[7:4]<->VP[03:0
129 < TDA1997X_VP24_V03_00
130
131 port {
132 tda1997x_to_ipu1_csi0_
133 remote-endpoin
134 bus-width = <1
135 hsync-active =
136 vsync-active =
137 data-active =
138 };
139 };
140 };
141 - VP[15:8] connected to IMX6 CSI_DATA[19:12]
142 16bit I2S layout0 with a 128*fs clock (A_WS
143 hdmi-receiver@48 {
144 compatible = "nxp,tda19971";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_tda1997x
147 reg = <0x48>;
148 interrupt-parent = <&gpio1>;
149 interrupts = <7 IRQ_TYPE_LEVEL
150 DOVDD-supply = <®_3p3v>;
151 AVDD-supply = <®_1p8v>;
152 DVDD-supply = <®_1p8v>;
153 /* audio */
154 #sound-dai-cells = <0>;
155 nxp,audout-format = "i2s";
156 nxp,audout-layout = <0>;
157 nxp,audout-width = <16>;
158 nxp,audout-mclk-fs = <128>;
159 /*
160 * The 8bpp BT656 mode outputs
161 * 2 pixclk cycles.
162 */
163 nxp,vidout-portcfg =
164 /* YCbCr[11:8]<->VP[15
165 < TDA1997X_VP24_V15_12
166 /* YCbCr[7:4]<->VP[11:
167 < TDA1997X_VP24_V11_08
168
169 port {
170 tda1997x_to_ipu1_csi0_
171 remote-endpoin
172 bus-width = <1
173 hsync-active =
174 vsync-active =
175 data-active =
176 };
177 };
178 };
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