1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/media/i2c/t 4 $id: http://devicetree.org/schemas/media/i2c/toshiba,tc358746.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Toshiba TC358746 Parallel to MIPI CSI2 7 title: Toshiba TC358746 Parallel to MIPI CSI2 Bridge
8 8
9 maintainers: 9 maintainers:
10 - Marco Felsch <kernel@pengutronix.de> 10 - Marco Felsch <kernel@pengutronix.de>
11 11
12 description: |- 12 description: |-
13 The Toshiba TC358746 converts a parallel vid 13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel 14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable throug 15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in - 16 interface is only supported in parallel-in -> csi-out mode.
17 17
18 Note that the current device tree bindings o 18 Note that the current device tree bindings only support the
19 parallel-in -> csi-out path. 19 parallel-in -> csi-out path.
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 const: toshiba,tc358746 23 const: toshiba,tc358746
24 24
25 reg: 25 reg:
26 maxItems: 1 26 maxItems: 1
27 27
28 clocks: 28 clocks:
29 description: 29 description:
30 The phandle to the reference clock sourc 30 The phandle to the reference clock source. This corresponds to the
31 hardware pin REFCLK. 31 hardware pin REFCLK.
32 maxItems: 1 32 maxItems: 1
33 33
34 clock-names: 34 clock-names:
35 const: refclk 35 const: refclk
36 36
37 "#clock-cells": 37 "#clock-cells":
38 description: | 38 description: |
39 The bridge can act as clock provider for 39 The bridge can act as clock provider for the sensor. To enable this
40 support #clock-cells must be specified. 40 support #clock-cells must be specified. Attention if this feature is used
41 then the mclk rate must be at least: (2 41 then the mclk rate must be at least: (2 * link-frequency) / 8
42 `-- 42 `------------------ยด ^
43 int 43 internal PLL rate smallest possible
44 44 mclk-div
45 const: 0 45 const: 0
46 46
47 clock-output-names: 47 clock-output-names:
48 description: 48 description:
49 The clock name of the MCLK output, the d 49 The clock name of the MCLK output, the default name is tc358746-mclk.
50 maxItems: 1 50 maxItems: 1
51 51
52 vddc-supply: 52 vddc-supply:
53 description: Digital core voltage supply, 53 description: Digital core voltage supply, 1.2 volts
54 54
55 vddio-supply: 55 vddio-supply:
56 description: Digital I/O voltage supply, 1 56 description: Digital I/O voltage supply, 1.8 volts
57 57
58 vddmipi-supply: 58 vddmipi-supply:
59 description: MIPI CSI phy voltage supply, 59 description: MIPI CSI phy voltage supply, 1.2 volts
60 60
61 reset-gpios: 61 reset-gpios:
62 description: 62 description:
63 The phandle and specifier for the GPIO t 63 The phandle and specifier for the GPIO that controls the chip reset.
64 This corresponds to the hardware pin RES 64 This corresponds to the hardware pin RESX which is physically active low.
65 maxItems: 1 65 maxItems: 1
66 66
67 ports: 67 ports:
68 $ref: /schemas/graph.yaml#/properties/port 68 $ref: /schemas/graph.yaml#/properties/ports
69 properties: 69 properties:
70 port@0: 70 port@0:
71 $ref: /schemas/graph.yaml#/$defs/port- 71 $ref: /schemas/graph.yaml#/$defs/port-base
72 unevaluatedProperties: false 72 unevaluatedProperties: false
73 description: Input port 73 description: Input port
74 74
75 properties: 75 properties:
76 endpoint: 76 endpoint:
77 $ref: /schemas/media/video-interfa 77 $ref: /schemas/media/video-interfaces.yaml#
78 unevaluatedProperties: false 78 unevaluatedProperties: false
79 79
80 properties: 80 properties:
81 hsync-active: true 81 hsync-active: true
82 vsync-active: true 82 vsync-active: true
83 bus-type: 83 bus-type:
84 enum: [ 5, 6 ] 84 enum: [ 5, 6 ]
85 85
86 required: 86 required:
87 - hsync-active 87 - hsync-active
88 - vsync-active 88 - vsync-active
89 - bus-type 89 - bus-type
90 90
91 port@1: 91 port@1:
92 $ref: /schemas/graph.yaml#/$defs/port- 92 $ref: /schemas/graph.yaml#/$defs/port-base
93 unevaluatedProperties: false 93 unevaluatedProperties: false
94 description: Output port 94 description: Output port
95 95
96 properties: 96 properties:
97 endpoint: 97 endpoint:
98 $ref: /schemas/media/video-interfa 98 $ref: /schemas/media/video-interfaces.yaml#
99 unevaluatedProperties: false 99 unevaluatedProperties: false
100 100
101 properties: 101 properties:
102 data-lanes: 102 data-lanes:
103 minItems: 1 103 minItems: 1
104 maxItems: 4 104 maxItems: 4
105 105
106 clock-noncontinuous: true 106 clock-noncontinuous: true
107 link-frequencies: true 107 link-frequencies: true
108 108
109 required: 109 required:
110 - data-lanes 110 - data-lanes
111 - link-frequencies 111 - link-frequencies
112 112
113 required: 113 required:
114 - port@0 114 - port@0
115 - port@1 115 - port@1
116 116
117 required: 117 required:
118 - compatible 118 - compatible
119 - reg 119 - reg
120 - clocks 120 - clocks
121 - clock-names 121 - clock-names
122 - vddc-supply 122 - vddc-supply
123 - vddio-supply 123 - vddio-supply
124 - vddmipi-supply 124 - vddmipi-supply
125 - ports 125 - ports
126 126
127 additionalProperties: false 127 additionalProperties: false
128 128
129 examples: 129 examples:
130 - | 130 - |
131 #include <dt-bindings/gpio/gpio.h> 131 #include <dt-bindings/gpio/gpio.h>
132 132
133 i2c { 133 i2c {
134 #address-cells = <1>; 134 #address-cells = <1>;
135 #size-cells = <0>; 135 #size-cells = <0>;
136 136
137 csi-bridge@e { 137 csi-bridge@e {
138 compatible = "toshiba,tc358746"; 138 compatible = "toshiba,tc358746";
139 reg = <0xe>; 139 reg = <0xe>;
140 140
141 clocks = <&refclk>; 141 clocks = <&refclk>;
142 clock-names = "refclk"; 142 clock-names = "refclk";
143 143
144 reset-gpios = <&gpio 2 GPIO_ACTIVE_LOW 144 reset-gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
145 145
146 vddc-supply = <&v1_2d>; 146 vddc-supply = <&v1_2d>;
147 vddio-supply = <&v1_8d>; 147 vddio-supply = <&v1_8d>;
148 vddmipi-supply = <&v1_2d>; 148 vddmipi-supply = <&v1_2d>;
149 149
150 /* sensor mclk provider */ 150 /* sensor mclk provider */
151 #clock-cells = <0>; 151 #clock-cells = <0>;
152 152
153 ports { 153 ports {
154 #address-cells = <1>; 154 #address-cells = <1>;
155 #size-cells = <0>; 155 #size-cells = <0>;
156 156
157 /* Input */ 157 /* Input */
158 port@0 { 158 port@0 {
159 reg = <0>; 159 reg = <0>;
160 tc358746_in: endpoint { 160 tc358746_in: endpoint {
161 remote-endpoint = <&sensor_out>; 161 remote-endpoint = <&sensor_out>;
162 hsync-active = <0>; 162 hsync-active = <0>;
163 vsync-active = <0>; 163 vsync-active = <0>;
164 bus-type = <5>; 164 bus-type = <5>;
165 }; 165 };
166 }; 166 };
167 167
168 /* Output */ 168 /* Output */
169 port@1 { 169 port@1 {
170 reg = <1>; 170 reg = <1>;
171 tc358746_out: endpoint { 171 tc358746_out: endpoint {
172 remote-endpoint = <&mipi_csi2_in 172 remote-endpoint = <&mipi_csi2_in>;
173 data-lanes = <1 2>; 173 data-lanes = <1 2>;
174 clock-noncontinuous; 174 clock-noncontinuous;
175 link-frequencies = /bits/ 64 <21 175 link-frequencies = /bits/ 64 <216000000>;
176 }; 176 };
177 }; 177 };
178 }; 178 };
179 }; 179 };
180 }; 180 };
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