1 Freescale i.MX Media Video Device 1 Freescale i.MX Media Video Device
2 ================================= 2 =================================
3 3
4 Video Media Controller node 4 Video Media Controller node
5 --------------------------- 5 ---------------------------
6 6
7 This is the media controller node for video ca 7 This is the media controller node for video capture support. It is a
8 virtual device that lists the camera serial in 8 virtual device that lists the camera serial interface nodes that the
9 media device will control. 9 media device will control.
10 10
11 Required properties: 11 Required properties:
12 - compatible : "fsl,imx-capture-subsystem"; 12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandl 13 - ports : Should contain a list of phandles pointing to camera
14 sensor interface ports of IPU 14 sensor interface ports of IPU devices
15 15
16 example: 16 example:
17 17
18 capture-subsystem { 18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsyste 19 compatible = "fsl,imx-capture-subsystem";
20 ports = <&ipu1_csi0>, <&ipu1_csi1>; 20 ports = <&ipu1_csi0>, <&ipu1_csi1>;
21 }; 21 };
22 22
23 23
24 mipi_csi2 node 24 mipi_csi2 node
25 -------------- 25 --------------
26 26
27 This is the device node for the MIPI CSI-2 Rec 27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same 29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-speci 30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
31 glue logic, also controlled from the same regi 31 glue logic, also controlled from the same register block. The CSI2IPU
32 gasket demultiplexes the four virtual channel 32 gasket demultiplexes the four virtual channel streams from the host
33 controller's 32-bit output image bus onto four 33 controller's 32-bit output image bus onto four 16-bit parallel busses
34 to the i.MX IPU CSIs. 34 to the i.MX IPU CSIs.
35 35
36 Required properties: 36 Required properties:
37 - compatible : "fsl,imx6-mipi-csi2"; 37 - compatible : "fsl,imx6-mipi-csi2";
38 - reg : physical base address and le 38 - reg : physical base address and length of the register set;
39 - clocks : the MIPI CSI-2 receiver requ 39 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
40 (the D-PHY clock), video_27m 40 (the D-PHY clock), video_27m (D-PHY PLL reference
41 clock), and eim_podf; 41 clock), and eim_podf;
42 - clock-names : must contain "dphy", "ref", 42 - clock-names : must contain "dphy", "ref", "pix";
43 - port@* : five port nodes must exist, 43 - port@* : five port nodes must exist, containing endpoints
44 connecting to the source and 44 connecting to the source and sink devices according to
45 of_graph bindings. The first 45 of_graph bindings. The first port is an input port,
46 connecting with a MIPI CSI-2 46 connecting with a MIPI CSI-2 source, and ports 1
47 through 4 are output ports c 47 through 4 are output ports connecting with parallel
48 bus sink endpoint nodes and 48 bus sink endpoint nodes and correspond to the four
49 MIPI CSI-2 virtual channel o 49 MIPI CSI-2 virtual channel outputs.
50 50
51 Optional properties: 51 Optional properties:
52 - interrupts : must contain two level-trigg 52 - interrupts : must contain two level-triggered interrupts,
53 in order: 100 and 101; 53 in order: 100 and 101;
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