1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/media/media 4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MediaTek Resizer 7 title: MediaTek Resizer
8 8
9 maintainers: 9 maintainers:
10 - Matthias Brugger <matthias.bgg@gmail.com> 10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com> 11 - Moudy Ho <moudy.ho@mediatek.com>
12 12
13 description: | 13 description: |
14 One of Media Data Path 3 (MDP3) components u 14 One of Media Data Path 3 (MDP3) components used to do frame resizing.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 oneOf: !! 18 items:
19 - enum: 19 - enum:
20 - mediatek,mt8183-mdp3-rsz 20 - mediatek,mt8183-mdp3-rsz
21 - items: <<
22 - enum: <<
23 - mediatek,mt8195-mdp3-rsz <<
24 - const: mediatek,mt8183-mdp3-rsz <<
25 21
26 reg: 22 reg:
27 maxItems: 1 23 maxItems: 1
28 24
29 mediatek,gce-client-reg: 25 mediatek,gce-client-reg:
30 $ref: /schemas/types.yaml#/definitions/pha 26 $ref: /schemas/types.yaml#/definitions/phandle-array
31 items: 27 items:
32 items: 28 items:
33 - description: phandle of GCE 29 - description: phandle of GCE
34 - description: GCE subsys id 30 - description: GCE subsys id
35 - description: register offset 31 - description: register offset
36 - description: register size 32 - description: register size
37 description: The register of client driver 33 description: The register of client driver can be configured by gce with
38 4 arguments defined in this property. Ea 34 4 arguments defined in this property. Each GCE subsys id is mapping to
39 a client defined in the header include/d 35 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
40 36
41 mediatek,gce-events: 37 mediatek,gce-events:
42 description: 38 description:
43 The event id which is mapping to the spe 39 The event id which is mapping to the specific hardware event signal
44 to gce. The event id is defined in the g 40 to gce. The event id is defined in the gce header
45 include/dt-bindings/gce/<chip>-gce.h of 41 include/dt-bindings/gce/<chip>-gce.h of each chips.
46 $ref: /schemas/types.yaml#/definitions/uin 42 $ref: /schemas/types.yaml#/definitions/uint32-array
47 43
48 clocks: 44 clocks:
49 minItems: 1 45 minItems: 1
50 46
51 required: 47 required:
52 - compatible 48 - compatible
53 - reg 49 - reg
54 - mediatek,gce-client-reg 50 - mediatek,gce-client-reg
55 - mediatek,gce-events 51 - mediatek,gce-events
56 - clocks 52 - clocks
57 53
58 additionalProperties: false 54 additionalProperties: false
59 55
60 examples: 56 examples:
61 - | 57 - |
62 #include <dt-bindings/clock/mt8183-clk.h> 58 #include <dt-bindings/clock/mt8183-clk.h>
63 #include <dt-bindings/gce/mt8183-gce.h> 59 #include <dt-bindings/gce/mt8183-gce.h>
64 60
65 mdp3_rsz0: mdp3-rsz0@14003000 { 61 mdp3_rsz0: mdp3-rsz0@14003000 {
66 compatible = "mediatek,mt8183-mdp3-rsz"; 62 compatible = "mediatek,mt8183-mdp3-rsz";
67 reg = <0x14003000 0x1000>; 63 reg = <0x14003000 0x1000>;
68 mediatek,gce-client-reg = <&gce SUBSYS_1 64 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
69 mediatek,gce-events = <CMDQ_EVENT_MDP_RS 65 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
70 <CMDQ_EVENT_MDP_RS 66 <CMDQ_EVENT_MDP_RSZ0_EOF>;
71 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 67 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
72 }; 68 };
73 69
74 mdp3_rsz1: mdp3-rsz1@14004000 { 70 mdp3_rsz1: mdp3-rsz1@14004000 {
75 compatible = "mediatek,mt8183-mdp3-rsz"; 71 compatible = "mediatek,mt8183-mdp3-rsz";
76 reg = <0x14004000 0x1000>; 72 reg = <0x14004000 0x1000>;
77 mediatek,gce-client-reg = <&gce SUBSYS_1 73 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
78 mediatek,gce-events = <CMDQ_EVENT_MDP_RS 74 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
79 <CMDQ_EVENT_MDP_RS 75 <CMDQ_EVENT_MDP_RSZ1_EOF>;
80 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 76 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
81 }; 77 };
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