1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 2
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/media/qcom, !! 5 $id: "http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#"
6 $schema: http://devicetree.org/meta-schemas/co !! 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 7
8 title: Qualcomm CAMSS ISP 8 title: Qualcomm CAMSS ISP
9 9
10 maintainers: 10 maintainers:
11 - Robert Foss <robert.foss@linaro.org> 11 - Robert Foss <robert.foss@linaro.org>
12 - AngeloGioacchino Del Regno <angelogioacchin 12 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
13 13
14 description: | 14 description: |
15 The CAMSS IP is a CSI decoder and ISP presen 15 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 const: qcom,sdm660-camss 19 const: qcom,sdm660-camss
20 20
21 clocks: 21 clocks:
22 minItems: 42 22 minItems: 42
23 maxItems: 42 23 maxItems: 42
24 24
25 clock-names: 25 clock-names:
26 items: 26 items:
27 - const: ahb 27 - const: ahb
28 - const: cphy_csid0 28 - const: cphy_csid0
29 - const: cphy_csid1 29 - const: cphy_csid1
30 - const: cphy_csid2 30 - const: cphy_csid2
31 - const: cphy_csid3 31 - const: cphy_csid3
32 - const: csi0_ahb 32 - const: csi0_ahb
33 - const: csi0 33 - const: csi0
34 - const: csi0_phy 34 - const: csi0_phy
35 - const: csi0_pix 35 - const: csi0_pix
36 - const: csi0_rdi 36 - const: csi0_rdi
37 - const: csi1_ahb 37 - const: csi1_ahb
38 - const: csi1 38 - const: csi1
39 - const: csi1_phy 39 - const: csi1_phy
40 - const: csi1_pix 40 - const: csi1_pix
41 - const: csi1_rdi 41 - const: csi1_rdi
42 - const: csi2_ahb 42 - const: csi2_ahb
43 - const: csi2 43 - const: csi2
44 - const: csi2_phy 44 - const: csi2_phy
45 - const: csi2_pix 45 - const: csi2_pix
46 - const: csi2_rdi 46 - const: csi2_rdi
47 - const: csi3_ahb 47 - const: csi3_ahb
48 - const: csi3 48 - const: csi3
49 - const: csi3_phy 49 - const: csi3_phy
50 - const: csi3_pix 50 - const: csi3_pix
51 - const: csi3_rdi 51 - const: csi3_rdi
52 - const: csiphy0_timer 52 - const: csiphy0_timer
53 - const: csiphy1_timer 53 - const: csiphy1_timer
54 - const: csiphy2_timer 54 - const: csiphy2_timer
55 - const: csiphy_ahb2crif 55 - const: csiphy_ahb2crif
56 - const: csi_vfe0 56 - const: csi_vfe0
57 - const: csi_vfe1 57 - const: csi_vfe1
58 - const: ispif_ahb 58 - const: ispif_ahb
59 - const: throttle_axi 59 - const: throttle_axi
60 - const: top_ahb 60 - const: top_ahb
61 - const: vfe0_ahb 61 - const: vfe0_ahb
62 - const: vfe0 62 - const: vfe0
63 - const: vfe0_stream 63 - const: vfe0_stream
64 - const: vfe1_ahb 64 - const: vfe1_ahb
65 - const: vfe1 65 - const: vfe1
66 - const: vfe1_stream 66 - const: vfe1_stream
67 - const: vfe_ahb 67 - const: vfe_ahb
68 - const: vfe_axi 68 - const: vfe_axi
69 69
70 interrupts: 70 interrupts:
71 minItems: 10 71 minItems: 10
72 maxItems: 10 72 maxItems: 10
73 73
74 interrupt-names: 74 interrupt-names:
75 items: 75 items:
76 - const: csid0 76 - const: csid0
77 - const: csid1 77 - const: csid1
78 - const: csid2 78 - const: csid2
79 - const: csid3 79 - const: csid3
80 - const: csiphy0 80 - const: csiphy0
81 - const: csiphy1 81 - const: csiphy1
82 - const: csiphy2 82 - const: csiphy2
83 - const: ispif 83 - const: ispif
84 - const: vfe0 84 - const: vfe0
85 - const: vfe1 85 - const: vfe1
86 86
87 interconnects: <<
88 maxItems: 1 <<
89 <<
90 interconnect-names: <<
91 items: <<
92 - const: vfe-mem <<
93 <<
94 iommus: 87 iommus:
95 maxItems: 4 88 maxItems: 4
96 89
97 power-domains: 90 power-domains:
98 items: 91 items:
99 - description: VFE0 GDSC - Video Front E 92 - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
100 - description: VFE1 GDSC - Video Front E 93 - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
101 94
102 ports: 95 ports:
103 $ref: /schemas/graph.yaml#/properties/port 96 $ref: /schemas/graph.yaml#/properties/ports
104 97
105 description: 98 description:
106 CSI input ports. 99 CSI input ports.
107 100
108 properties: 101 properties:
109 port@0: 102 port@0:
110 $ref: /schemas/graph.yaml#/$defs/port- 103 $ref: /schemas/graph.yaml#/$defs/port-base
111 unevaluatedProperties: false 104 unevaluatedProperties: false
112 description: 105 description:
113 Input port for receiving CSI data. 106 Input port for receiving CSI data.
114 107
115 properties: 108 properties:
116 endpoint: 109 endpoint:
117 $ref: video-interfaces.yaml# 110 $ref: video-interfaces.yaml#
118 unevaluatedProperties: false 111 unevaluatedProperties: false
119 112
120 properties: 113 properties:
>> 114 clock-lanes:
>> 115 items:
>> 116 - const: 7
>> 117
121 data-lanes: 118 data-lanes:
122 minItems: 1 119 minItems: 1
123 maxItems: 4 120 maxItems: 4
124 121
125 required: 122 required:
>> 123 - clock-lanes
126 - data-lanes 124 - data-lanes
127 125
128 port@1: 126 port@1:
129 $ref: /schemas/graph.yaml#/$defs/port- 127 $ref: /schemas/graph.yaml#/$defs/port-base
130 unevaluatedProperties: false 128 unevaluatedProperties: false
131 description: 129 description:
132 Input port for receiving CSI data. 130 Input port for receiving CSI data.
133 131
134 properties: 132 properties:
135 endpoint: 133 endpoint:
136 $ref: video-interfaces.yaml# 134 $ref: video-interfaces.yaml#
137 unevaluatedProperties: false 135 unevaluatedProperties: false
138 136
139 properties: 137 properties:
>> 138 clock-lanes:
>> 139 items:
>> 140 - const: 7
>> 141
140 data-lanes: 142 data-lanes:
141 minItems: 1 143 minItems: 1
142 maxItems: 4 144 maxItems: 4
143 145
144 required: 146 required:
>> 147 - clock-lanes
145 - data-lanes 148 - data-lanes
146 149
147 port@2: 150 port@2:
148 $ref: /schemas/graph.yaml#/$defs/port- 151 $ref: /schemas/graph.yaml#/$defs/port-base
149 unevaluatedProperties: false 152 unevaluatedProperties: false
150 description: 153 description:
151 Input port for receiving CSI data. 154 Input port for receiving CSI data.
152 155
153 properties: 156 properties:
154 endpoint: 157 endpoint:
155 $ref: video-interfaces.yaml# 158 $ref: video-interfaces.yaml#
156 unevaluatedProperties: false 159 unevaluatedProperties: false
157 160
158 properties: 161 properties:
>> 162 clock-lanes:
>> 163 items:
>> 164 - const: 7
>> 165
159 data-lanes: 166 data-lanes:
160 minItems: 1 167 minItems: 1
161 maxItems: 4 168 maxItems: 4
162 169
163 required: 170 required:
>> 171 - clock-lanes
164 - data-lanes 172 - data-lanes
165 173
166 port@3: 174 port@3:
167 $ref: /schemas/graph.yaml#/$defs/port- 175 $ref: /schemas/graph.yaml#/$defs/port-base
168 unevaluatedProperties: false 176 unevaluatedProperties: false
169 description: 177 description:
170 Input port for receiving CSI data. 178 Input port for receiving CSI data.
171 179
172 properties: 180 properties:
173 endpoint: 181 endpoint:
174 $ref: video-interfaces.yaml# 182 $ref: video-interfaces.yaml#
175 unevaluatedProperties: false 183 unevaluatedProperties: false
176 184
177 properties: 185 properties:
>> 186 clock-lanes:
>> 187 items:
>> 188 - const: 7
>> 189
178 data-lanes: 190 data-lanes:
179 minItems: 1 191 minItems: 1
180 maxItems: 4 192 maxItems: 4
181 193
182 required: 194 required:
>> 195 - clock-lanes
183 - data-lanes 196 - data-lanes
184 197
185 reg: 198 reg:
186 minItems: 14 199 minItems: 14
187 maxItems: 14 200 maxItems: 14
188 201
189 reg-names: 202 reg-names:
190 items: 203 items:
191 - const: csi_clk_mux 204 - const: csi_clk_mux
192 - const: csid0 205 - const: csid0
193 - const: csid1 206 - const: csid1
194 - const: csid2 207 - const: csid2
195 - const: csid3 208 - const: csid3
196 - const: csiphy0 209 - const: csiphy0
197 - const: csiphy0_clk_mux 210 - const: csiphy0_clk_mux
198 - const: csiphy1 211 - const: csiphy1
199 - const: csiphy1_clk_mux 212 - const: csiphy1_clk_mux
200 - const: csiphy2 213 - const: csiphy2
201 - const: csiphy2_clk_mux 214 - const: csiphy2_clk_mux
202 - const: ispif 215 - const: ispif
203 - const: vfe0 216 - const: vfe0
204 - const: vfe1 217 - const: vfe1
205 218
206 vdda-supply: 219 vdda-supply:
207 description: 220 description:
208 Definition of the regulator used as anal 221 Definition of the regulator used as analog power supply.
209 222
210 required: 223 required:
211 - clock-names 224 - clock-names
212 - clocks 225 - clocks
213 - compatible 226 - compatible
214 - interrupt-names 227 - interrupt-names
215 - interrupts 228 - interrupts
216 - iommus 229 - iommus
217 - power-domains 230 - power-domains
218 - reg 231 - reg
219 - reg-names 232 - reg-names
220 - vdda-supply 233 - vdda-supply
221 234
222 additionalProperties: false 235 additionalProperties: false
223 236
224 examples: 237 examples:
225 - | 238 - |
226 #include <dt-bindings/interrupt-controller 239 #include <dt-bindings/interrupt-controller/arm-gic.h>
227 #include <dt-bindings/clock/qcom,gcc-sdm66 240 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
228 #include <dt-bindings/clock/qcom,mmcc-sdm6 241 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
229 242
230 camss: camss@ca00020 { !! 243 camss: camss@ca00000 {
231 compatible = "qcom,sdm660-camss"; 244 compatible = "qcom,sdm660-camss";
232 245
233 clocks = <&mmcc CAMSS_AHB_CLK>, 246 clocks = <&mmcc CAMSS_AHB_CLK>,
234 <&mmcc CAMSS_CPHY_CSID0_CLK>, 247 <&mmcc CAMSS_CPHY_CSID0_CLK>,
235 <&mmcc CAMSS_CPHY_CSID1_CLK>, 248 <&mmcc CAMSS_CPHY_CSID1_CLK>,
236 <&mmcc CAMSS_CPHY_CSID2_CLK>, 249 <&mmcc CAMSS_CPHY_CSID2_CLK>,
237 <&mmcc CAMSS_CPHY_CSID3_CLK>, 250 <&mmcc CAMSS_CPHY_CSID3_CLK>,
238 <&mmcc CAMSS_CSI0_AHB_CLK>, 251 <&mmcc CAMSS_CSI0_AHB_CLK>,
239 <&mmcc CAMSS_CSI0_CLK>, 252 <&mmcc CAMSS_CSI0_CLK>,
240 <&mmcc CAMSS_CPHY_CSID0_CLK>, 253 <&mmcc CAMSS_CPHY_CSID0_CLK>,
241 <&mmcc CAMSS_CSI0PIX_CLK>, 254 <&mmcc CAMSS_CSI0PIX_CLK>,
242 <&mmcc CAMSS_CSI0RDI_CLK>, 255 <&mmcc CAMSS_CSI0RDI_CLK>,
243 <&mmcc CAMSS_CSI1_AHB_CLK>, 256 <&mmcc CAMSS_CSI1_AHB_CLK>,
244 <&mmcc CAMSS_CSI1_CLK>, 257 <&mmcc CAMSS_CSI1_CLK>,
245 <&mmcc CAMSS_CPHY_CSID1_CLK>, 258 <&mmcc CAMSS_CPHY_CSID1_CLK>,
246 <&mmcc CAMSS_CSI1PIX_CLK>, 259 <&mmcc CAMSS_CSI1PIX_CLK>,
247 <&mmcc CAMSS_CSI1RDI_CLK>, 260 <&mmcc CAMSS_CSI1RDI_CLK>,
248 <&mmcc CAMSS_CSI2_AHB_CLK>, 261 <&mmcc CAMSS_CSI2_AHB_CLK>,
249 <&mmcc CAMSS_CSI2_CLK>, 262 <&mmcc CAMSS_CSI2_CLK>,
250 <&mmcc CAMSS_CPHY_CSID2_CLK>, 263 <&mmcc CAMSS_CPHY_CSID2_CLK>,
251 <&mmcc CAMSS_CSI2PIX_CLK>, 264 <&mmcc CAMSS_CSI2PIX_CLK>,
252 <&mmcc CAMSS_CSI2RDI_CLK>, 265 <&mmcc CAMSS_CSI2RDI_CLK>,
253 <&mmcc CAMSS_CSI3_AHB_CLK>, 266 <&mmcc CAMSS_CSI3_AHB_CLK>,
254 <&mmcc CAMSS_CSI3_CLK>, 267 <&mmcc CAMSS_CSI3_CLK>,
255 <&mmcc CAMSS_CPHY_CSID3_CLK>, 268 <&mmcc CAMSS_CPHY_CSID3_CLK>,
256 <&mmcc CAMSS_CSI3PIX_CLK>, 269 <&mmcc CAMSS_CSI3PIX_CLK>,
257 <&mmcc CAMSS_CSI3RDI_CLK>, 270 <&mmcc CAMSS_CSI3RDI_CLK>,
258 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 271 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
259 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 272 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
260 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 273 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
261 <&mmcc CSIPHY_AHB2CRIF_CLK>, 274 <&mmcc CSIPHY_AHB2CRIF_CLK>,
262 <&mmcc CAMSS_CSI_VFE0_CLK>, 275 <&mmcc CAMSS_CSI_VFE0_CLK>,
263 <&mmcc CAMSS_CSI_VFE1_CLK>, 276 <&mmcc CAMSS_CSI_VFE1_CLK>,
264 <&mmcc CAMSS_ISPIF_AHB_CLK>, 277 <&mmcc CAMSS_ISPIF_AHB_CLK>,
265 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 278 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
266 <&mmcc CAMSS_TOP_AHB_CLK>, 279 <&mmcc CAMSS_TOP_AHB_CLK>,
267 <&mmcc CAMSS_VFE0_AHB_CLK>, 280 <&mmcc CAMSS_VFE0_AHB_CLK>,
268 <&mmcc CAMSS_VFE0_CLK>, 281 <&mmcc CAMSS_VFE0_CLK>,
269 <&mmcc CAMSS_VFE0_STREAM_CLK>, 282 <&mmcc CAMSS_VFE0_STREAM_CLK>,
270 <&mmcc CAMSS_VFE1_AHB_CLK>, 283 <&mmcc CAMSS_VFE1_AHB_CLK>,
271 <&mmcc CAMSS_VFE1_CLK>, 284 <&mmcc CAMSS_VFE1_CLK>,
272 <&mmcc CAMSS_VFE1_STREAM_CLK>, 285 <&mmcc CAMSS_VFE1_STREAM_CLK>,
273 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 286 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
274 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 287 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
275 288
276 clock-names = "ahb", 289 clock-names = "ahb",
277 "cphy_csid0", 290 "cphy_csid0",
278 "cphy_csid1", 291 "cphy_csid1",
279 "cphy_csid2", 292 "cphy_csid2",
280 "cphy_csid3", 293 "cphy_csid3",
281 "csi0_ahb", 294 "csi0_ahb",
282 "csi0", 295 "csi0",
283 "csi0_phy", 296 "csi0_phy",
284 "csi0_pix", 297 "csi0_pix",
285 "csi0_rdi", 298 "csi0_rdi",
286 "csi1_ahb", 299 "csi1_ahb",
287 "csi1", 300 "csi1",
288 "csi1_phy", 301 "csi1_phy",
289 "csi1_pix", 302 "csi1_pix",
290 "csi1_rdi", 303 "csi1_rdi",
291 "csi2_ahb", 304 "csi2_ahb",
292 "csi2", 305 "csi2",
293 "csi2_phy", 306 "csi2_phy",
294 "csi2_pix", 307 "csi2_pix",
295 "csi2_rdi", 308 "csi2_rdi",
296 "csi3_ahb", 309 "csi3_ahb",
297 "csi3", 310 "csi3",
298 "csi3_phy", 311 "csi3_phy",
299 "csi3_pix", 312 "csi3_pix",
300 "csi3_rdi", 313 "csi3_rdi",
301 "csiphy0_timer", 314 "csiphy0_timer",
302 "csiphy1_timer", 315 "csiphy1_timer",
303 "csiphy2_timer", 316 "csiphy2_timer",
304 "csiphy_ahb2crif", 317 "csiphy_ahb2crif",
305 "csi_vfe0", 318 "csi_vfe0",
306 "csi_vfe1", 319 "csi_vfe1",
307 "ispif_ahb", 320 "ispif_ahb",
308 "throttle_axi", 321 "throttle_axi",
309 "top_ahb", 322 "top_ahb",
310 "vfe0_ahb", 323 "vfe0_ahb",
311 "vfe0", 324 "vfe0",
312 "vfe0_stream", 325 "vfe0_stream",
313 "vfe1_ahb", 326 "vfe1_ahb",
314 "vfe1", 327 "vfe1",
315 "vfe1_stream", 328 "vfe1_stream",
316 "vfe_ahb", 329 "vfe_ahb",
317 "vfe_axi"; 330 "vfe_axi";
318 331
319 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_ 332 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
320 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 333 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
321 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 334 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
322 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 335 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
323 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 336 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
324 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 337 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
325 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 338 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
326 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 339 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
327 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 340 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 341 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
329 342
330 interrupt-names = "csid0", 343 interrupt-names = "csid0",
331 "csid1", 344 "csid1",
332 "csid2", 345 "csid2",
333 "csid3", 346 "csid3",
334 "csiphy0", 347 "csiphy0",
335 "csiphy1", 348 "csiphy1",
336 "csiphy2", 349 "csiphy2",
337 "ispif", 350 "ispif",
338 "vfe0", 351 "vfe0",
339 "vfe1"; 352 "vfe1";
340 353
341 iommus = <&mmss_smmu 0xc00>, 354 iommus = <&mmss_smmu 0xc00>,
342 <&mmss_smmu 0xc01>, 355 <&mmss_smmu 0xc01>,
343 <&mmss_smmu 0xc02>, 356 <&mmss_smmu 0xc02>,
344 <&mmss_smmu 0xc03>; 357 <&mmss_smmu 0xc03>;
345 358
346 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 359 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
347 <&mmcc CAMSS_VFE1_GDSC>; 360 <&mmcc CAMSS_VFE1_GDSC>;
348 361
349 reg = <0x0ca00020 0x10>, 362 reg = <0x0ca00020 0x10>,
350 <0x0ca30000 0x100>, 363 <0x0ca30000 0x100>,
351 <0x0ca30400 0x100>, 364 <0x0ca30400 0x100>,
352 <0x0ca30800 0x100>, 365 <0x0ca30800 0x100>,
353 <0x0ca30c00 0x100>, 366 <0x0ca30c00 0x100>,
354 <0x0c824000 0x1000>, 367 <0x0c824000 0x1000>,
355 <0x0ca00120 0x4>, 368 <0x0ca00120 0x4>,
356 <0x0c825000 0x1000>, 369 <0x0c825000 0x1000>,
357 <0x0ca00124 0x4>, 370 <0x0ca00124 0x4>,
358 <0x0c826000 0x1000>, 371 <0x0c826000 0x1000>,
359 <0x0ca00128 0x4>, 372 <0x0ca00128 0x4>,
360 <0x0ca31000 0x500>, 373 <0x0ca31000 0x500>,
361 <0x0ca10000 0x1000>, 374 <0x0ca10000 0x1000>,
362 <0x0ca14000 0x1000>; 375 <0x0ca14000 0x1000>;
363 376
364 reg-names = "csi_clk_mux", 377 reg-names = "csi_clk_mux",
365 "csid0", 378 "csid0",
366 "csid1", 379 "csid1",
367 "csid2", 380 "csid2",
368 "csid3", 381 "csid3",
369 "csiphy0", 382 "csiphy0",
370 "csiphy0_clk_mux", 383 "csiphy0_clk_mux",
371 "csiphy1", 384 "csiphy1",
372 "csiphy1_clk_mux", 385 "csiphy1_clk_mux",
373 "csiphy2", 386 "csiphy2",
374 "csiphy2_clk_mux", 387 "csiphy2_clk_mux",
375 "ispif", 388 "ispif",
376 "vfe0", 389 "vfe0",
377 "vfe1"; 390 "vfe1";
378 391
379 vdda-supply = <®_2v8>; 392 vdda-supply = <®_2v8>;
380 393
381 ports { 394 ports {
382 #address-cells = <1>; 395 #address-cells = <1>;
383 #size-cells = <0>; 396 #size-cells = <0>;
384 }; 397 };
385 }; 398 };
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