1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 %YAML 1.2 2 %YAML 1.2 3 --- 3 --- 4 $id: http://devicetree.org/schemas/media/renes 4 $id: http://devicetree.org/schemas/media/renesas,vsp1.yaml# 5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 title: Renesas VSP Video Processing Engine 7 title: Renesas VSP Video Processing Engine 8 8 9 maintainers: 9 maintainers: 10 - Laurent Pinchart <laurent.pinchart@ideasonb 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11 11 12 description: 12 description: 13 The VSP is a video processing engine that su 13 The VSP is a video processing engine that supports up-/down-scaling, alpha 14 blending, color space conversion and various 14 blending, color space conversion and various other image processing features. 15 It can be found in the Renesas R-Car Gen2, R 15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs. 16 16 17 properties: 17 properties: 18 compatible: 18 compatible: 19 oneOf: !! 19 enum: 20 - enum: !! 20 - renesas,r9a07g044-vsp2 # RZ/G2L 21 - renesas,r9a07g044-vsp2 # RZ/G2L !! 21 - renesas,vsp1 # R-Car Gen2 and RZ/G1 22 - renesas,vsp1 # R-Car Gen2 and RZ/G !! 22 - renesas,vsp2 # R-Car Gen3 and RZ/G2 23 - renesas,vsp2 # R-Car Gen3 and RZ/G << 24 - items: << 25 - enum: << 26 - renesas,r9a07g043u-vsp2 # RZ << 27 - renesas,r9a07g054-vsp2 # RZ << 28 - const: renesas,r9a07g044-vsp2 # RZ << 29 23 30 reg: 24 reg: 31 maxItems: 1 25 maxItems: 1 32 26 33 interrupts: 27 interrupts: 34 maxItems: 1 28 maxItems: 1 35 29 36 clocks: true 30 clocks: true 37 clock-names: true 31 clock-names: true 38 32 39 power-domains: 33 power-domains: 40 maxItems: 1 34 maxItems: 1 41 35 42 resets: 36 resets: 43 maxItems: 1 37 maxItems: 1 44 38 45 renesas,fcp: 39 renesas,fcp: 46 $ref: /schemas/types.yaml#/definitions/pha 40 $ref: /schemas/types.yaml#/definitions/phandle 47 description: 41 description: 48 A phandle referencing the FCP that handl 42 A phandle referencing the FCP that handles memory accesses for the VSP. 49 43 50 required: 44 required: 51 - compatible 45 - compatible 52 - reg 46 - reg 53 - interrupts 47 - interrupts 54 - clocks 48 - clocks 55 - power-domains 49 - power-domains 56 - resets 50 - resets 57 51 58 additionalProperties: false 52 additionalProperties: false 59 53 60 allOf: 54 allOf: 61 - if: 55 - if: 62 properties: 56 properties: 63 compatible: 57 compatible: 64 contains: 58 contains: 65 const: renesas,vsp1 59 const: renesas,vsp1 66 then: 60 then: 67 properties: 61 properties: 68 renesas,fcp: false 62 renesas,fcp: false 69 else: 63 else: 70 required: 64 required: 71 - renesas,fcp 65 - renesas,fcp 72 66 73 - if: 67 - if: 74 properties: 68 properties: 75 compatible: 69 compatible: 76 contains: 70 contains: 77 const: renesas,r9a07g044-vsp2 71 const: renesas,r9a07g044-vsp2 78 then: 72 then: 79 properties: 73 properties: 80 clocks: 74 clocks: 81 items: 75 items: 82 - description: Main clock 76 - description: Main clock 83 - description: Register access clo 77 - description: Register access clock 84 - description: Video clock 78 - description: Video clock 85 clock-names: 79 clock-names: 86 items: 80 items: 87 - const: aclk 81 - const: aclk 88 - const: pclk 82 - const: pclk 89 - const: vclk 83 - const: vclk 90 required: 84 required: 91 - clock-names 85 - clock-names 92 else: 86 else: 93 properties: 87 properties: 94 clocks: 88 clocks: 95 maxItems: 1 89 maxItems: 1 96 clock-names: false 90 clock-names: false 97 91 98 examples: 92 examples: 99 # R8A7790 (R-Car H2) VSP1-S 93 # R8A7790 (R-Car H2) VSP1-S 100 - | 94 - | 101 #include <dt-bindings/clock/renesas-cpg-ms 95 #include <dt-bindings/clock/renesas-cpg-mssr.h> 102 #include <dt-bindings/interrupt-controller 96 #include <dt-bindings/interrupt-controller/arm-gic.h> 103 #include <dt-bindings/power/r8a7790-sysc.h 97 #include <dt-bindings/power/r8a7790-sysc.h> 104 98 105 vsp@fe928000 { 99 vsp@fe928000 { 106 compatible = "renesas,vsp1"; 100 compatible = "renesas,vsp1"; 107 reg = <0xfe928000 0x8000>; 101 reg = <0xfe928000 0x8000>; 108 interrupts = <GIC_SPI 267 IRQ_TYPE_LEV 102 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&cpg CPG_MOD 131>; 103 clocks = <&cpg CPG_MOD 131>; 110 power-domains = <&sysc R8A7790_PD_ALWA 104 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 111 resets = <&cpg 131>; 105 resets = <&cpg 131>; 112 }; 106 }; 113 107 114 # R8A77951 (R-Car H3) VSP2-BC 108 # R8A77951 (R-Car H3) VSP2-BC 115 - | 109 - | 116 #include <dt-bindings/clock/renesas-cpg-ms 110 #include <dt-bindings/clock/renesas-cpg-mssr.h> 117 #include <dt-bindings/interrupt-controller 111 #include <dt-bindings/interrupt-controller/arm-gic.h> 118 #include <dt-bindings/power/r8a7795-sysc.h 112 #include <dt-bindings/power/r8a7795-sysc.h> 119 113 120 vsp@fe920000 { 114 vsp@fe920000 { 121 compatible = "renesas,vsp2"; 115 compatible = "renesas,vsp2"; 122 reg = <0xfe920000 0x8000>; 116 reg = <0xfe920000 0x8000>; 123 interrupts = <GIC_SPI 465 IRQ_TYPE_LEV 117 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&cpg CPG_MOD 624>; 118 clocks = <&cpg CPG_MOD 624>; 125 power-domains = <&sysc R8A7795_PD_A3VP 119 power-domains = <&sysc R8A7795_PD_A3VP>; 126 resets = <&cpg 624>; 120 resets = <&cpg 624>; 127 121 128 renesas,fcp = <&fcpvb1>; 122 renesas,fcp = <&fcpvb1>; 129 }; 123 }; 130 ... 124 ...
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