1 STMicroelectronics STi c8sectpfe binding 1 STMicroelectronics STi c8sectpfe binding 2 ============================================ 2 ============================================ 3 3 4 This document describes the c8sectpfe device b 4 This document describes the c8sectpfe device bindings that is used to get transport 5 stream data into the SoC on the TS pins, and i 5 stream data into the SoC on the TS pins, and into DDR for further processing. 6 6 7 It is typically used in conjunction with one o 7 It is typically used in conjunction with one or more demodulator and tuner devices 8 which converts from the RF to digital domain. 8 which converts from the RF to digital domain. Demodulators and tuners are usually 9 located on an external DVB frontend card conne 9 located on an external DVB frontend card connected to SoC TS input pins. 10 10 11 Currently 7 TS input (tsin) channels are suppo 11 Currently 7 TS input (tsin) channels are supported on the stih407 family SoC. 12 12 13 Required properties (controller (parent) node) 13 Required properties (controller (parent) node): 14 - compatible : Should be "stih407-c8sectpfe 14 - compatible : Should be "stih407-c8sectpfe" 15 15 16 - reg : Address and length of regist 16 - reg : Address and length of register sets for each device in 17 "reg-names" 17 "reg-names" 18 18 19 - reg-names : The names of the register ad 19 - reg-names : The names of the register addresses corresponding to the 20 registers filled in "reg": 20 registers filled in "reg": 21 - c8sectpfe: c8sectpfe 21 - c8sectpfe: c8sectpfe registers 22 - c8sectpfe-ram: c8sec 22 - c8sectpfe-ram: c8sectpfe internal sram 23 23 24 - clocks : phandle list of c8sectpfe cl 24 - clocks : phandle list of c8sectpfe clocks 25 - clock-names : should be "c8sectpfe" 25 - clock-names : should be "c8sectpfe" 26 See: Documentation/devicetree/bindings/clock/c 26 See: Documentation/devicetree/bindings/clock/clock-bindings.txt 27 27 28 - pinctrl-names : a pinctrl state named tsin%d 28 - pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num) 29 must be defined for each ts 29 must be defined for each tsin child node. 30 - pinctrl-0 : phandle referencing pin conf 30 - pinctrl-0 : phandle referencing pin configuration for this tsin configuration 31 See: Documentation/devicetree/bindings/pinctrl !! 31 See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt 32 32 33 33 34 Required properties (tsin (child) node): 34 Required properties (tsin (child) node): 35 35 36 - tsin-num : tsin id of the InputBlock (m 36 - tsin-num : tsin id of the InputBlock (must be between 0 to 6) 37 - i2c-bus : phandle to the I2C bus DT no 37 - i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected. 38 - reset-gpios : reset gpio for this tsin cha !! 38 - rst-gpio : reset gpio for this tsin channel. 39 39 40 Optional properties (tsin (child) node): 40 Optional properties (tsin (child) node): 41 41 42 - invert-ts-clk : Bool property to con 42 - invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk). 43 - serial-not-parallel : Bool property to con 43 - serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>). 44 - async-not-sync : Bool property to con 44 - async-not-sync : Bool property to control if data is received in asynchronous mode 45 (all bits/bytes wit 45 (all bits/bytes with ts_valid or ts_packet asserted are valid). 46 46 47 - dvb-card : Describes the NIM ca 47 - dvb-card : Describes the NIM card connected to this tsin channel. 48 48 49 Example: 49 Example: 50 50 51 /* stih410 SoC b2120 + b2004a + stv0367-pll(NI 51 /* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */ 52 52 53 c8sectpfe@8a20000 { !! 53 c8sectpfe@08a20000 { 54 compatible = "st,stih407-c8sec 54 compatible = "st,stih407-c8sectpfe"; >> 55 status = "okay"; 55 reg = <0x08a20000 0x10000>, <0 56 reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>; 56 reg-names = "stfe", "stfe-ram" 57 reg-names = "stfe", "stfe-ram"; 57 interrupts = <GIC_SPI 34 IRQ_T !! 58 interrupts = <0 34 0>, <0 35 0>; 58 interrupt-names = "stfe-error- 59 interrupt-names = "stfe-error-irq", "stfe-idle-irq"; >> 60 >> 61 pinctrl-names = "tsin0-serial", "tsin0-parallel", "tsin3-serial", >> 62 "tsin4-serial", "tsin5-serial"; >> 63 59 pinctrl-0 = <&pinctrl_ts 64 pinctrl-0 = <&pinctrl_tsin0_serial>; 60 pinctrl-1 = <&pinctrl_ts 65 pinctrl-1 = <&pinctrl_tsin0_parallel>; 61 pinctrl-2 = <&pinctrl_ts 66 pinctrl-2 = <&pinctrl_tsin3_serial>; 62 pinctrl-3 = <&pinctrl_ts 67 pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; 63 pinctrl-4 = <&pinctrl_ts 68 pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; 64 pinctrl-names = "tsin0-seria !! 69 65 "tsin0-paral << 66 "tsin3-seria << 67 "tsin4-seria << 68 "tsin5-seria << 69 clocks = <&clk_s_c0_flexgen CL 70 clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; 70 clock-names = "c8sectpfe"; !! 71 clock-names = "stfe"; 71 72 72 /* tsin0 is TSA on NIMA */ 73 /* tsin0 is TSA on NIMA */ 73 tsin0: port@0 { 74 tsin0: port@0 { 74 tsin-num 75 tsin-num = <0>; 75 serial-not-parallel; 76 serial-not-parallel; 76 i2c-bus 77 i2c-bus = <&ssc2>; 77 reset-gpios !! 78 rst-gpio = <&pio15 4 0>; 78 dvb-card 79 dvb-card = <STV0367_TDA18212_NIMA_1>; 79 }; 80 }; 80 81 81 tsin3: port@3 { 82 tsin3: port@3 { 82 tsin-num 83 tsin-num = <3>; 83 serial-not-parallel; 84 serial-not-parallel; 84 i2c-bus 85 i2c-bus = <&ssc3>; 85 reset-gpios !! 86 rst-gpio = <&pio15 7 0>; 86 dvb-card 87 dvb-card = <STV0367_TDA18212_NIMB_1>; 87 }; 88 }; 88 }; 89 };
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