1 DT bindings for Xilinx video IP cores
2 -------------------------------------
3
4 Xilinx video IP cores process video streams by
5 sources. They are connected by links through t
6 creating a video pipeline.
7
8 Each video IP core is represented by an AMBA b
9 tree using bindings documented in this directo
10 cores are represented as defined in ../video-i
11
12 The whole pipeline is represented by an AMBA
13 tree using bindings documented in ./xlnx,video
14
15 Common properties
16 -----------------
17
18 The following properties are common to all Xil
19
20 - xlnx,video-format: This property represents
21 AXI bus between video IP cores, using its VF
22 Video IP and System Design Guide" [UG934]. H
23 core is described in the IP core bindings do
24
25 - xlnx,video-width: This property qualifies th
26 width expressed as a number of bits per pixe
27 use the same width.
28
29 - xlnx,cfa-pattern: When the video format is s
30 describes the sensor's color filter array pa
31 "bggr", "gbrg", "grbg", "rggb" and "mono". I
32 defaults to "mono".
33
34
35 [UG934] https://www.xilinx.com/support/documen
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