1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # %YAML 1.2 2 # %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/memory-cont 4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip rk3399 DMC (Dynamic Memory Con 7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
8 8
9 maintainers: 9 maintainers:
10 - Brian Norris <briannorris@chromium.org> 10 - Brian Norris <briannorris@chromium.org>
11 11
12 properties: 12 properties:
13 compatible: 13 compatible:
14 enum: 14 enum:
15 - rockchip,rk3399-dmc 15 - rockchip,rk3399-dmc
16 16
17 devfreq-events: 17 devfreq-events:
18 $ref: /schemas/types.yaml#/definitions/pha 18 $ref: /schemas/types.yaml#/definitions/phandle
19 description: 19 description:
20 Node to get DDR loading. Refer to 20 Node to get DDR loading. Refer to
21 Documentation/devicetree/bindings/devfre 21 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml.
22 22
23 clocks: 23 clocks:
24 maxItems: 1 24 maxItems: 1
25 25
26 clock-names: 26 clock-names:
27 items: 27 items:
28 - const: dmc_clk 28 - const: dmc_clk
29 29
30 operating-points-v2: true 30 operating-points-v2: true
31 31
32 center-supply: 32 center-supply:
33 description: 33 description:
34 DMC regulator supply. 34 DMC regulator supply.
35 35
36 rockchip,pmu: 36 rockchip,pmu:
37 $ref: /schemas/types.yaml#/definitions/pha 37 $ref: /schemas/types.yaml#/definitions/phandle
38 description: 38 description:
39 Phandle to the syscon managing the "PMU 39 Phandle to the syscon managing the "PMU general register files".
40 40
41 interrupts: 41 interrupts:
42 maxItems: 1 42 maxItems: 1
43 description: 43 description:
44 The CPU interrupt number. It should be a 44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
45 finishes, a DCF interrupt is triggered. 45 finishes, a DCF interrupt is triggered.
46 46
47 rockchip,ddr3_speed_bin: 47 rockchip,ddr3_speed_bin:
48 deprecated: true 48 deprecated: true
49 $ref: /schemas/types.yaml#/definitions/uin 49 $ref: /schemas/types.yaml#/definitions/uint32
50 description: 50 description:
51 For values, reference include/dt-binding 51 For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
52 DDR3 cl-trp-trcd type. It must be set ac 52 DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
53 datasheet; DO NOT use a smaller "Speed B 53 datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
54 being used. 54 being used.
55 55
56 rockchip,pd_idle: 56 rockchip,pd_idle:
57 deprecated: true 57 deprecated: true
58 $ref: /schemas/types.yaml#/definitions/uin 58 $ref: /schemas/types.yaml#/definitions/uint32
59 description: 59 description:
60 Configure the PD_IDLE value. Defines the 60 Configure the PD_IDLE value. Defines the power-down idle period in which
61 memories are placed into power-down mode 61 memories are placed into power-down mode if bus is idle for PD_IDLE DFI
62 clock cycles. 62 clock cycles.
63 See also rockchip,pd-idle-ns. 63 See also rockchip,pd-idle-ns.
64 64
65 rockchip,sr_idle: 65 rockchip,sr_idle:
66 deprecated: true 66 deprecated: true
67 $ref: /schemas/types.yaml#/definitions/uin 67 $ref: /schemas/types.yaml#/definitions/uint32
68 description: 68 description:
69 Configure the SR_IDLE value. Defines the 69 Configure the SR_IDLE value. Defines the self-refresh idle period in
70 which memories are placed into self-refr 70 which memories are placed into self-refresh mode if bus is idle for
71 SR_IDLE * 1024 DFI clock cycles (DFI clo 71 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
72 See also rockchip,sr-idle-ns. 72 See also rockchip,sr-idle-ns.
73 default: 0 73 default: 0
74 74
75 rockchip,sr_mc_gate_idle: 75 rockchip,sr_mc_gate_idle:
76 deprecated: true 76 deprecated: true
77 $ref: /schemas/types.yaml#/definitions/uin 77 $ref: /schemas/types.yaml#/definitions/uint32
78 description: 78 description:
79 Defines the memory self-refresh and cont 79 Defines the memory self-refresh and controller clock gating idle period.
80 Memories are placed into self-refresh mo 80 Memories are placed into self-refresh mode and memory controller clock
81 arg gating started if bus is idle for sr 81 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
82 cycles. 82 cycles.
83 See also rockchip,sr-mc-gate-idle-ns. 83 See also rockchip,sr-mc-gate-idle-ns.
84 84
85 rockchip,srpd_lite_idle: 85 rockchip,srpd_lite_idle:
86 deprecated: true 86 deprecated: true
87 $ref: /schemas/types.yaml#/definitions/uin 87 $ref: /schemas/types.yaml#/definitions/uint32
88 description: 88 description:
89 Defines the self-refresh power down idle 89 Defines the self-refresh power down idle period in which memories are
90 placed into self-refresh power down mode 90 placed into self-refresh power down mode if bus is idle for
91 srpd_lite_idle * 1024 DFI clock cycles. 91 srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
92 only. 92 only.
93 See also rockchip,srpd-lite-idle-ns. 93 See also rockchip,srpd-lite-idle-ns.
94 94
95 rockchip,standby_idle: 95 rockchip,standby_idle:
96 deprecated: true 96 deprecated: true
97 $ref: /schemas/types.yaml#/definitions/uin 97 $ref: /schemas/types.yaml#/definitions/uint32
98 description: 98 description:
99 Defines the standby idle period in which 99 Defines the standby idle period in which memories are placed into
100 self-refresh mode. The controller, pi, P 100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
101 if bus is idle for standby_idle * DFI cl 101 if bus is idle for standby_idle * DFI clock cycles.
102 See also rockchip,standby-idle-ns. 102 See also rockchip,standby-idle-ns.
103 103
104 rockchip,dram_dll_dis_freq: 104 rockchip,dram_dll_dis_freq:
105 deprecated: true 105 deprecated: true
106 $ref: /schemas/types.yaml#/definitions/uin 106 $ref: /schemas/types.yaml#/definitions/uint32
107 description: | 107 description: |
108 Defines the DDR3 DLL bypass frequency in 108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will b 109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
110 Note: if DLL was bypassed, the odt will 110 Note: if DLL was bypassed, the odt will also stop working.
111 111
112 rockchip,phy_dll_dis_freq: 112 rockchip,phy_dll_dis_freq:
113 deprecated: true 113 deprecated: true
114 $ref: /schemas/types.yaml#/definitions/uin 114 $ref: /schemas/types.yaml#/definitions/uint32
115 description: | 115 description: |
116 Defines the PHY dll bypass frequency in 116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
117 is less than DRAM_DLL_DISB_FREQ, PHY DLL 117 is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
118 Note: PHY DLL and PHY ODT are independen 118 Note: PHY DLL and PHY ODT are independent.
119 119
120 rockchip,auto_pd_dis_freq: 120 rockchip,auto_pd_dis_freq:
121 deprecated: true 121 deprecated: true
122 $ref: /schemas/types.yaml#/definitions/uin 122 $ref: /schemas/types.yaml#/definitions/uint32
123 description: 123 description:
124 Defines the auto PD disable frequency in 124 Defines the auto PD disable frequency in MHz.
125 125
126 rockchip,ddr3_odt_dis_freq: 126 rockchip,ddr3_odt_dis_freq:
127 $ref: /schemas/types.yaml#/definitions/uin 127 $ref: /schemas/types.yaml#/definitions/uint32
128 minimum: 1000000 # In case anyone thought 128 minimum: 1000000 # In case anyone thought this was MHz.
129 description: 129 description:
130 When the DRAM type is DDR3, this paramet 130 When the DRAM type is DDR3, this parameter defines the ODT disable
131 frequency in Hz. When the DDR frequency 131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
132 the ODT on the DRAM side and controller 132 the ODT on the DRAM side and controller side are both disabled.
133 133
134 rockchip,ddr3_drv: 134 rockchip,ddr3_drv:
135 deprecated: true 135 deprecated: true
136 $ref: /schemas/types.yaml#/definitions/uin 136 $ref: /schemas/types.yaml#/definitions/uint32
137 description: 137 description:
138 When the DRAM type is DDR3, this paramet 138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
139 strength in ohms. 139 strength in ohms.
140 default: 40 140 default: 40
141 141
142 rockchip,ddr3_odt: 142 rockchip,ddr3_odt:
143 deprecated: true 143 deprecated: true
144 $ref: /schemas/types.yaml#/definitions/uin 144 $ref: /schemas/types.yaml#/definitions/uint32
145 description: 145 description:
146 When the DRAM type is DDR3, this paramet 146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
147 strength in ohms. 147 strength in ohms.
148 default: 120 148 default: 120
149 149
150 rockchip,phy_ddr3_ca_drv: 150 rockchip,phy_ddr3_ca_drv:
151 deprecated: true 151 deprecated: true
152 $ref: /schemas/types.yaml#/definitions/uin 152 $ref: /schemas/types.yaml#/definitions/uint32
153 description: 153 description:
154 When the DRAM type is DDR3, this paramet 154 When the DRAM type is DDR3, this parameter defines the phy side CA line
155 (including command line, address line an 155 (including command line, address line and clock line) drive strength.
156 default: 40 156 default: 40
157 157
158 rockchip,phy_ddr3_dq_drv: 158 rockchip,phy_ddr3_dq_drv:
159 deprecated: true 159 deprecated: true
160 $ref: /schemas/types.yaml#/definitions/uin 160 $ref: /schemas/types.yaml#/definitions/uint32
161 description: 161 description:
162 When the DRAM type is DDR3, this paramet 162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
163 (including DQS/DQ/DM line) drive strengt 163 (including DQS/DQ/DM line) drive strength.
164 default: 40 164 default: 40
165 165
166 rockchip,phy_ddr3_odt: 166 rockchip,phy_ddr3_odt:
167 deprecated: true 167 deprecated: true
168 $ref: /schemas/types.yaml#/definitions/uin 168 $ref: /schemas/types.yaml#/definitions/uint32
169 description: 169 description:
170 When the DRAM type is DDR3, this paramet 170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
171 strength. 171 strength.
172 default: 240 172 default: 240
173 173
174 rockchip,lpddr3_odt_dis_freq: 174 rockchip,lpddr3_odt_dis_freq:
175 $ref: /schemas/types.yaml#/definitions/uin 175 $ref: /schemas/types.yaml#/definitions/uint32
176 minimum: 1000000 # In case anyone thought 176 minimum: 1000000 # In case anyone thought this was MHz.
177 description: 177 description:
178 When the DRAM type is LPDDR3, this param 178 When the DRAM type is LPDDR3, this parameter defines then ODT disable
179 frequency in Hz. When DDR frequency is l 179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
180 ODT on the DRAM side and controller side 180 ODT on the DRAM side and controller side are both disabled.
181 181
182 rockchip,lpddr3_drv: 182 rockchip,lpddr3_drv:
183 deprecated: true 183 deprecated: true
184 $ref: /schemas/types.yaml#/definitions/uin 184 $ref: /schemas/types.yaml#/definitions/uint32
185 description: 185 description:
186 When the DRAM type is LPDDR3, this param 186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
187 strength in ohms. 187 strength in ohms.
188 default: 34 188 default: 34
189 189
190 rockchip,lpddr3_odt: 190 rockchip,lpddr3_odt:
191 deprecated: true 191 deprecated: true
192 $ref: /schemas/types.yaml#/definitions/uin 192 $ref: /schemas/types.yaml#/definitions/uint32
193 description: 193 description:
194 When the DRAM type is LPDDR3, this param 194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
195 strength in ohms. 195 strength in ohms.
196 default: 240 196 default: 240
197 197
198 rockchip,phy_lpddr3_ca_drv: 198 rockchip,phy_lpddr3_ca_drv:
199 deprecated: true 199 deprecated: true
200 $ref: /schemas/types.yaml#/definitions/uin 200 $ref: /schemas/types.yaml#/definitions/uint32
201 description: 201 description:
202 When the DRAM type is LPDDR3, this param 202 When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
203 (including command line, address line an 203 (including command line, address line and clock line) drive strength.
204 default: 40 204 default: 40
205 205
206 rockchip,phy_lpddr3_dq_drv: 206 rockchip,phy_lpddr3_dq_drv:
207 deprecated: true 207 deprecated: true
208 $ref: /schemas/types.yaml#/definitions/uin 208 $ref: /schemas/types.yaml#/definitions/uint32
209 description: 209 description:
210 When the DRAM type is LPDDR3, this param 210 When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
211 (including DQS/DQ/DM line) drive strengt 211 (including DQS/DQ/DM line) drive strength.
212 default: 40 212 default: 40
213 213
214 rockchip,phy_lpddr3_odt: 214 rockchip,phy_lpddr3_odt:
215 deprecated: true 215 deprecated: true
216 $ref: /schemas/types.yaml#/definitions/uin 216 $ref: /schemas/types.yaml#/definitions/uint32
217 description: 217 description:
218 When dram type is LPDDR3, this parameter 218 When dram type is LPDDR3, this parameter define the phy side odt
219 strength, default value is 240. 219 strength, default value is 240.
220 220
221 rockchip,lpddr4_odt_dis_freq: 221 rockchip,lpddr4_odt_dis_freq:
222 $ref: /schemas/types.yaml#/definitions/uin 222 $ref: /schemas/types.yaml#/definitions/uint32
223 minimum: 1000000 # In case anyone thought 223 minimum: 1000000 # In case anyone thought this was MHz.
224 description: 224 description:
225 When the DRAM type is LPDDR4, this param 225 When the DRAM type is LPDDR4, this parameter defines the ODT disable
226 frequency in Hz. When the DDR frequency 226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
227 the ODT on the DRAM side and controller 227 the ODT on the DRAM side and controller side are both disabled.
228 228
229 rockchip,lpddr4_drv: 229 rockchip,lpddr4_drv:
230 deprecated: true 230 deprecated: true
231 $ref: /schemas/types.yaml#/definitions/uin 231 $ref: /schemas/types.yaml#/definitions/uint32
232 description: 232 description:
233 When the DRAM type is LPDDR4, this param 233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
234 strength in ohms. 234 strength in ohms.
235 default: 60 235 default: 60
236 236
237 rockchip,lpddr4_dq_odt: 237 rockchip,lpddr4_dq_odt:
238 deprecated: true 238 deprecated: true
239 $ref: /schemas/types.yaml#/definitions/uin 239 $ref: /schemas/types.yaml#/definitions/uint32
240 description: 240 description:
241 When the DRAM type is LPDDR4, this param 241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
242 DQS/DQ line strength in ohms. 242 DQS/DQ line strength in ohms.
243 default: 40 243 default: 40
244 244
245 rockchip,lpddr4_ca_odt: 245 rockchip,lpddr4_ca_odt:
246 deprecated: true 246 deprecated: true
247 $ref: /schemas/types.yaml#/definitions/uin 247 $ref: /schemas/types.yaml#/definitions/uint32
248 description: 248 description:
249 When the DRAM type is LPDDR4, this param 249 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
250 CA line strength in ohms. 250 CA line strength in ohms.
251 default: 40 251 default: 40
252 252
253 rockchip,phy_lpddr4_ca_drv: 253 rockchip,phy_lpddr4_ca_drv:
254 deprecated: true 254 deprecated: true
255 $ref: /schemas/types.yaml#/definitions/uin 255 $ref: /schemas/types.yaml#/definitions/uint32
256 description: 256 description:
257 When the DRAM type is LPDDR4, this param 257 When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
258 (including command address line) drive s 258 (including command address line) drive strength.
259 default: 40 259 default: 40
260 260
261 rockchip,phy_lpddr4_ck_cs_drv: 261 rockchip,phy_lpddr4_ck_cs_drv:
262 deprecated: true 262 deprecated: true
263 $ref: /schemas/types.yaml#/definitions/uin 263 $ref: /schemas/types.yaml#/definitions/uint32
264 description: 264 description:
265 When the DRAM type is LPDDR4, this param 265 When the DRAM type is LPDDR4, this parameter defines the PHY side clock
266 line and CS line drive strength. 266 line and CS line drive strength.
267 default: 80 267 default: 80
268 268
269 rockchip,phy_lpddr4_dq_drv: 269 rockchip,phy_lpddr4_dq_drv:
270 deprecated: true 270 deprecated: true
271 $ref: /schemas/types.yaml#/definitions/uin 271 $ref: /schemas/types.yaml#/definitions/uint32
272 description: 272 description:
273 When the DRAM type is LPDDR4, this param 273 When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
274 (including DQS/DQ/DM line) drive strengt 274 (including DQS/DQ/DM line) drive strength.
275 default: 80 275 default: 80
276 276
277 rockchip,phy_lpddr4_odt: 277 rockchip,phy_lpddr4_odt:
278 deprecated: true 278 deprecated: true
279 $ref: /schemas/types.yaml#/definitions/uin 279 $ref: /schemas/types.yaml#/definitions/uint32
280 description: 280 description:
281 When the DRAM type is LPDDR4, this param 281 When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
282 strength. 282 strength.
283 default: 60 283 default: 60
284 284
285 rockchip,pd-idle-ns: 285 rockchip,pd-idle-ns:
286 description: 286 description:
287 Configure the PD_IDLE value in nanosecon 287 Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
288 period in which memories are placed into 288 period in which memories are placed into power-down mode if bus is idle
289 for PD_IDLE nanoseconds. 289 for PD_IDLE nanoseconds.
290 290
291 rockchip,sr-idle-ns: 291 rockchip,sr-idle-ns:
292 description: 292 description:
293 Configure the SR_IDLE value in nanosecon 293 Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
294 period in which memories are placed into 294 period in which memories are placed into self-refresh mode if bus is idle
295 for SR_IDLE nanoseconds. 295 for SR_IDLE nanoseconds.
296 default: 0 296 default: 0
297 297
298 rockchip,sr-mc-gate-idle-ns: 298 rockchip,sr-mc-gate-idle-ns:
299 description: 299 description:
300 Defines the memory self-refresh and cont 300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
301 Memories are placed into self-refresh mo 301 Memories are placed into self-refresh mode and memory controller clock
302 arg gating started if bus is idle for sr 302 arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
303 303
304 rockchip,srpd-lite-idle-ns: 304 rockchip,srpd-lite-idle-ns:
305 description: 305 description:
306 Defines the self-refresh power down idle 306 Defines the self-refresh power down idle period in which memories are
307 placed into self-refresh power down mode 307 placed into self-refresh power down mode if bus is idle for
308 srpd_lite_idle nanoseconds. This paramet 308 srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.
309 309
310 rockchip,standby-idle-ns: 310 rockchip,standby-idle-ns:
311 description: 311 description:
312 Defines the standby idle period in which 312 Defines the standby idle period in which memories are placed into
313 self-refresh mode. The controller, pi, P 313 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
314 if bus is idle for standby_idle nanoseco 314 if bus is idle for standby_idle nanoseconds.
315 315
316 rockchip,pd-idle-dis-freq-hz: 316 rockchip,pd-idle-dis-freq-hz:
317 description: 317 description:
318 Defines the power-down idle disable freq 318 Defines the power-down idle disable frequency in Hz. When the DDR
319 frequency is greater than pd-idle-dis-fr 319 frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
320 See also rockchip,pd-idle-ns. 320 See also rockchip,pd-idle-ns.
321 321
322 rockchip,sr-idle-dis-freq-hz: 322 rockchip,sr-idle-dis-freq-hz:
323 description: 323 description:
324 Defines the self-refresh idle disable fr 324 Defines the self-refresh idle disable frequency in Hz. When the DDR
325 frequency is greater than sr-idle-dis-fr 325 frequency is greater than sr-idle-dis-freq, self-refresh idle is
326 disabled. See also rockchip,sr-idle-ns. 326 disabled. See also rockchip,sr-idle-ns.
327 327
328 rockchip,sr-mc-gate-idle-dis-freq-hz: 328 rockchip,sr-mc-gate-idle-dis-freq-hz:
329 description: 329 description:
330 Defines the self-refresh and memory-cont 330 Defines the self-refresh and memory-controller clock gating disable
331 frequency in Hz. When the DDR frequency 331 frequency in Hz. When the DDR frequency is greater than
332 sr-mc-gate-idle-dis-freq, the clock will 332 sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
333 rockchip,sr-mc-gate-idle-ns. 333 rockchip,sr-mc-gate-idle-ns.
334 334
335 rockchip,srpd-lite-idle-dis-freq-hz: 335 rockchip,srpd-lite-idle-dis-freq-hz:
336 description: 336 description:
337 Defines the self-refresh power down idle 337 Defines the self-refresh power down idle disable frequency in Hz. When
338 the DDR frequency is greater than srpd-l 338 the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
339 not be placed into self-refresh power do 339 not be placed into self-refresh power down mode when idle. See also
340 rockchip,srpd-lite-idle-ns. 340 rockchip,srpd-lite-idle-ns.
341 341
342 rockchip,standby-idle-dis-freq-hz: 342 rockchip,standby-idle-dis-freq-hz:
343 description: 343 description:
344 Defines the standby idle disable frequen 344 Defines the standby idle disable frequency in Hz. When the DDR frequency
345 is greater than standby-idle-dis-freq, s 345 is greater than standby-idle-dis-freq, standby idle is disabled. See also
346 rockchip,standby-idle-ns. 346 rockchip,standby-idle-ns.
347 347
348 required: 348 required:
349 - compatible 349 - compatible
350 - devfreq-events 350 - devfreq-events
351 - clocks 351 - clocks
352 - clock-names 352 - clock-names
353 - operating-points-v2 353 - operating-points-v2
354 - center-supply 354 - center-supply
355 355
356 additionalProperties: false 356 additionalProperties: false
357 357
358 examples: 358 examples:
359 - | 359 - |
360 #include <dt-bindings/clock/rk3399-cru.h> 360 #include <dt-bindings/clock/rk3399-cru.h>
361 #include <dt-bindings/interrupt-controller 361 #include <dt-bindings/interrupt-controller/arm-gic.h>
362 memory-controller { 362 memory-controller {
363 compatible = "rockchip,rk3399-dmc"; 363 compatible = "rockchip,rk3399-dmc";
364 devfreq-events = <&dfi>; 364 devfreq-events = <&dfi>;
365 rockchip,pmu = <&pmu>; 365 rockchip,pmu = <&pmu>;
366 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_H 366 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&cru SCLK_DDRC>; 367 clocks = <&cru SCLK_DDRC>;
368 clock-names = "dmc_clk"; 368 clock-names = "dmc_clk";
369 operating-points-v2 = <&dmc_opp_table>; 369 operating-points-v2 = <&dmc_opp_table>;
370 center-supply = <&ppvar_centerlogic>; 370 center-supply = <&ppvar_centerlogic>;
371 rockchip,pd-idle-ns = <160>; 371 rockchip,pd-idle-ns = <160>;
372 rockchip,sr-idle-ns = <10240>; 372 rockchip,sr-idle-ns = <10240>;
373 rockchip,sr-mc-gate-idle-ns = <40960>; 373 rockchip,sr-mc-gate-idle-ns = <40960>;
374 rockchip,srpd-lite-idle-ns = <61440>; 374 rockchip,srpd-lite-idle-ns = <61440>;
375 rockchip,standby-idle-ns = <81920>; 375 rockchip,standby-idle-ns = <81920>;
376 rockchip,ddr3_odt_dis_freq = <333000000> 376 rockchip,ddr3_odt_dis_freq = <333000000>;
377 rockchip,lpddr3_odt_dis_freq = <33300000 377 rockchip,lpddr3_odt_dis_freq = <333000000>;
378 rockchip,lpddr4_odt_dis_freq = <33300000 378 rockchip,lpddr4_odt_dis_freq = <333000000>;
379 rockchip,pd-idle-dis-freq-hz = <10000000 379 rockchip,pd-idle-dis-freq-hz = <1000000000>;
380 rockchip,sr-idle-dis-freq-hz = <10000000 380 rockchip,sr-idle-dis-freq-hz = <1000000000>;
381 rockchip,sr-mc-gate-idle-dis-freq-hz = < 381 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
382 rockchip,srpd-lite-idle-dis-freq-hz = <0 382 rockchip,srpd-lite-idle-dis-freq-hz = <0>;
383 rockchip,standby-idle-dis-freq-hz = <928 383 rockchip,standby-idle-dis-freq-hz = <928000000>;
384 }; 384 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.