1 MAX77620 Power management IC from Maxim Semico 1 MAX77620 Power management IC from Maxim Semiconductor.
2 2
3 Required properties: 3 Required properties:
4 ------------------- 4 -------------------
5 - compatible: Must be one of 5 - compatible: Must be one of
6 "maxim,max77620" 6 "maxim,max77620"
7 "maxim,max20024" 7 "maxim,max20024"
8 "maxim,max77663" 8 "maxim,max77663"
9 - reg: I2C device address. 9 - reg: I2C device address.
10 10
11 Optional properties: 11 Optional properties:
12 ------------------- 12 -------------------
13 - interrupts: The interrupt on the p 13 - interrupts: The interrupt on the parent the controller is
14 connected to. 14 connected to.
15 - interrupt-controller: Marks the device node 15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage 16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interru 17 variant of <../interrupt-controller/interrupts.txt>
18 IRQ numbers for differ 18 IRQ numbers for different interrupt source of MAX77620
19 are defined at dt-bind 19 are defined at dt-bindings/mfd/max77620.h.
20 20
21 - system-power-controller: Indicates that this 21 - system-power-controller: Indicates that this PMIC is controlling the
22 system power, see [ 22 system power, see [1] for more details.
23 23
24 [1] Documentation/devicetree/bindings/power/po 24 [1] Documentation/devicetree/bindings/power/power-controller.txt
25 25
26 Optional subnodes and their properties: 26 Optional subnodes and their properties:
27 ======================================= 27 =======================================
28 28
29 Flexible power sequence configurations: 29 Flexible power sequence configurations:
30 -------------------------------------- 30 --------------------------------------
31 The Flexible Power Sequencer (FPS) allows each 31 The Flexible Power Sequencer (FPS) allows each regulator to power up under
32 hardware or software control. Additionally, ea 32 hardware or software control. Additionally, each regulator can power on
33 independently or among a group of other regula 33 independently or among a group of other regulators with an adjustable power-up
34 and power-down delays (sequencing). GPIO1, GPI 34 and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
35 to be part of a sequence allowing external reg 35 to be part of a sequence allowing external regulators to be sequenced along
36 with internal regulators. 32KHz clock can be p 36 with internal regulators. 32KHz clock can be programmed to be part of a
37 sequence. 37 sequence.
38 38
39 The flexible sequencing structure consists of 39 The flexible sequencing structure consists of two hardware enable inputs
40 (EN0, EN1), and 3 master sequencing timers cal 40 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.
41 Each master sequencing timer is programmable t 41 Each master sequencing timer is programmable through its configuration
42 register to have a hardware enable source (EN1 42 register to have a hardware enable source (EN1 or EN2) or a software enable
43 source (SW). When enabled/disabled, the master 43 source (SW). When enabled/disabled, the master sequencing timer generates
44 eight sequencing events on different time peri 44 eight sequencing events on different time periods called slots. The time
45 period between each event is programmable with 45 period between each event is programmable within the configuration register.
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz 46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
47 sequence slave register which allows its enabl 47 sequence slave register which allows its enable source to be specified as
48 a flexible power sequencer timer or a software 48 a flexible power sequencer timer or a software bit. When a FPS source of
49 regulators, GPIOs and clocks specifies the ena 49 regulators, GPIOs and clocks specifies the enable source to be a flexible
50 power sequencer, the power up and power down d 50 power sequencer, the power up and power down delays can be specified in
51 the regulators, GPIOs and clocks flexible powe 51 the regulators, GPIOs and clocks flexible power sequencer configuration
52 registers. 52 registers.
53 53
54 When FPS event cleared (set to LOW), regulator 54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
55 clock are set into following state at the sequ 55 clock are set into following state at the sequencing event that
56 corresponds to its flexible sequencer configur 56 corresponds to its flexible sequencer configuration register.
57 Sleep state: In thi 57 Sleep state: In this state, regulators, GPIOs
58 and 32 58 and 32KHz clock get disabled at
59 the se 59 the sequencing event.
60 Global Low Power Mode (GLPM): In thi 60 Global Low Power Mode (GLPM): In this state, regulators are set in
61 low po 61 low power mode at the sequencing event.
62 62
63 The configuration parameters of FPS is provide 63 The configuration parameters of FPS is provided through sub-node "fps"
64 and their child for FPS specific. The child no 64 and their child for FPS specific. The child node name for FPS are "fps0",
65 "fps1", and "fps2" for FPS0, FPS1 and FPS2 res 65 "fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
66 66
67 The FPS configurations like FPS source, power 67 The FPS configurations like FPS source, power up and power down slots for
68 regulators, GPIOs and 32kHz clocks are provide 68 regulators, GPIOs and 32kHz clocks are provided in their respective
69 configuration nodes which is explained in resp 69 configuration nodes which is explained in respective sub-system DT
70 binding document. 70 binding document.
71 71
72 There is need for different FPS configuration 72 There is need for different FPS configuration parameters based on system
73 state like when system state changed from acti 73 state like when system state changed from active to suspend or active to
74 power off (shutdown). 74 power off (shutdown).
75 75
76 Optional properties: 76 Optional properties:
77 ------------------- 77 -------------------
78 -maxim,fps-event-source: u32, F 78 -maxim,fps-event-source: u32, FPS event source like external
79 hardwa 79 hardware input to PMIC i.e. EN0, EN1 or
80 softwa 80 software (SW).
81 The ma 81 The macros are defined on
82 82 dt-bindings/mfd/max77620.h
83 for di 83 for different control source.
84 - MAX7 84 - MAX77620_FPS_EVENT_SRC_EN0
85 85 for hardware input pin EN0.
86 - MAX7 86 - MAX77620_FPS_EVENT_SRC_EN1
87 87 for hardware input pin EN1.
88 - MAX7 88 - MAX77620_FPS_EVENT_SRC_SW
89 89 for software control.
90 90
91 -maxim,shutdown-fps-time-period-us: u32, F 91 -maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds
92 when s 92 when system enters in to shutdown
93 state. 93 state.
94 94
95 -maxim,suspend-fps-time-period-us: u32, F 95 -maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds
96 when s 96 when system enters in to suspend state.
97 97
98 -maxim,device-state-on-disabled-event: u32, d 98 -maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS
99 event 99 event cleared (set to LOW) whether it
100 should 100 should go to sleep state or low-power
101 state. 101 state. Following are valid values:
102 - MAX7 102 - MAX77620_FPS_INACTIVE_STATE_SLEEP
103 103 to set the PMIC state to sleep.
104 - MAX7 104 - MAX77620_FPS_INACTIVE_STATE_LOW_POWER
105 105 to set the PMIC state to low
106 106 power.
107 Absenc 107 Absence of this property or other value
108 will n 108 will not change device state when FPS
109 event 109 event get cleared.
110 110
111 Here supported time periods by device in micro 111 Here supported time periods by device in microseconds are as follows:
112 MAX77620 supports 40, 80, 160, 320, 640, 1280, 112 MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
113 MAX20024 supports 20, 40, 80, 160, 320, 640, 1 113 MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
114 MAX77663 supports 20, 40, 80, 160, 320, 640, 1 114 MAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
115 115
116 -maxim,power-ok-control: configure map power o 116 -maxim,power-ok-control: configure map power ok bit
117 1: Enables POK(Power O 117 1: Enables POK(Power OK) to control nRST_IO and GPIO1
118 POK function. 118 POK function.
119 0: Disables POK contro 119 0: Disables POK control.
120 if property missing, d 120 if property missing, do not configure MPOK bit.
121 If POK mapping is enab 121 If POK mapping is enabled for GPIO1/nRST_IO then,
122 GPIO1/nRST_IO pins are 122 GPIO1/nRST_IO pins are HIGH only if all rails
123 that have POK control 123 that have POK control enabled are HIGH.
124 If any of the rails go 124 If any of the rails goes down(which are enabled for POK
125 control) then, GPIO1/n 125 control) then, GPIO1/nRST_IO goes LOW.
126 this property is valid 126 this property is valid for max20024 only.
127 127
128 For DT binding details of different sub module 128 For DT binding details of different sub modules like GPIO, pincontrol,
129 regulator, power, please refer respective devi 129 regulator, power, please refer respective device-tree binding document
130 under their respective sub-system directories. 130 under their respective sub-system directories.
131 131
132 Example: 132 Example:
133 -------- 133 --------
134 #include <dt-bindings/mfd/max77620.h> 134 #include <dt-bindings/mfd/max77620.h>
135 135
136 max77620@3c { 136 max77620@3c {
137 compatible = "maxim,max77620"; 137 compatible = "maxim,max77620";
138 reg = <0x3c>; 138 reg = <0x3c>;
139 139
140 interrupt-parent = <&intc>; 140 interrupt-parent = <&intc>;
141 interrupts = <0 86 IRQ_TYPE_NONE>; 141 interrupts = <0 86 IRQ_TYPE_NONE>;
142 142
143 interrupt-controller; 143 interrupt-controller;
144 #interrupt-cells = <2>; 144 #interrupt-cells = <2>;
145 145
146 fps { 146 fps {
147 fps0 { 147 fps0 {
148 maxim,shutdown-fps-tim 148 maxim,shutdown-fps-time-period-us = <1280>;
149 maxim,fps-event-source 149 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
150 }; 150 };
151 151
152 fps1 { 152 fps1 {
153 maxim,shutdown-fps-tim 153 maxim,shutdown-fps-time-period-us = <1280>;
154 maxim,fps-event-source 154 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
155 }; 155 };
156 156
157 fps2 { 157 fps2 {
158 maxim,shutdown-fps-tim 158 maxim,shutdown-fps-time-period-us = <1280>;
159 maxim,fps-event-source 159 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
160 }; 160 };
161 }; 161 };
162 }; 162 };
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