1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mmc/cdns,sd 4 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Cadence SD/SDIO/eMMC Host Controller (S 7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
8 8
9 maintainers: 9 maintainers:
10 - Masahiro Yamada <yamada.masahiro@socionext. 10 - Masahiro Yamada <yamada.masahiro@socionext.com>
>> 11 - Piotr Sroka <piotrs@cadence.com>
>> 12
>> 13 allOf:
>> 14 - $ref: mmc-controller.yaml
11 15
12 properties: 16 properties:
13 compatible: 17 compatible:
14 items: 18 items:
15 - enum: 19 - enum:
16 - amd,pensando-elba-sd4hc <<
17 - microchip,mpfs-sd4hc 20 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc 21 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc 22 - const: cdns,sd4hc
20 23
21 reg: 24 reg:
22 minItems: 1 !! 25 maxItems: 1
23 maxItems: 2 <<
24 26
25 interrupts: 27 interrupts:
26 maxItems: 1 28 maxItems: 1
27 29
28 clocks: 30 clocks:
29 maxItems: 1 31 maxItems: 1
30 32
31 resets: <<
32 maxItems: 1 <<
33 <<
34 # PHY DLL input delays: 33 # PHY DLL input delays:
35 # They are used to delay the data valid wind 34 # They are used to delay the data valid window, and align the window to
36 # sampling clock. The delay starts from 5ns 35 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
37 # and it is increased by 2.5ns in each step. 36 # and it is increased by 2.5ns in each step.
38 37
39 cdns,phy-input-delay-sd-highspeed: 38 cdns,phy-input-delay-sd-highspeed:
40 description: Value of the delay in the inp 39 description: Value of the delay in the input path for SD high-speed timing
41 $ref: /schemas/types.yaml#/definitions/uin !! 40 $ref: "/schemas/types.yaml#/definitions/uint32"
42 minimum: 0 41 minimum: 0
43 maximum: 0x1f 42 maximum: 0x1f
44 43
45 cdns,phy-input-delay-legacy: 44 cdns,phy-input-delay-legacy:
46 description: Value of the delay in the inp 45 description: Value of the delay in the input path for legacy timing
47 $ref: /schemas/types.yaml#/definitions/uin !! 46 $ref: "/schemas/types.yaml#/definitions/uint32"
48 minimum: 0 47 minimum: 0
49 maximum: 0x1f 48 maximum: 0x1f
50 49
51 cdns,phy-input-delay-sd-uhs-sdr12: 50 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the inp 51 description: Value of the delay in the input path for SD UHS SDR12 timing
53 $ref: /schemas/types.yaml#/definitions/uin !! 52 $ref: "/schemas/types.yaml#/definitions/uint32"
54 minimum: 0 53 minimum: 0
55 maximum: 0x1f 54 maximum: 0x1f
56 55
57 cdns,phy-input-delay-sd-uhs-sdr25: 56 cdns,phy-input-delay-sd-uhs-sdr25:
58 description: Value of the delay in the inp 57 description: Value of the delay in the input path for SD UHS SDR25 timing
59 $ref: /schemas/types.yaml#/definitions/uin !! 58 $ref: "/schemas/types.yaml#/definitions/uint32"
60 minimum: 0 59 minimum: 0
61 maximum: 0x1f 60 maximum: 0x1f
62 61
63 cdns,phy-input-delay-sd-uhs-sdr50: 62 cdns,phy-input-delay-sd-uhs-sdr50:
64 description: Value of the delay in the inp 63 description: Value of the delay in the input path for SD UHS SDR50 timing
65 $ref: /schemas/types.yaml#/definitions/uin !! 64 $ref: "/schemas/types.yaml#/definitions/uint32"
66 minimum: 0 65 minimum: 0
67 maximum: 0x1f 66 maximum: 0x1f
68 67
69 cdns,phy-input-delay-sd-uhs-ddr50: 68 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the inp 69 description: Value of the delay in the input path for SD UHS DDR50 timing
71 $ref: /schemas/types.yaml#/definitions/uin !! 70 $ref: "/schemas/types.yaml#/definitions/uint32"
72 minimum: 0 71 minimum: 0
73 maximum: 0x1f 72 maximum: 0x1f
74 73
75 cdns,phy-input-delay-mmc-highspeed: 74 cdns,phy-input-delay-mmc-highspeed:
76 description: Value of the delay in the inp 75 description: Value of the delay in the input path for MMC high-speed timing
77 $ref: /schemas/types.yaml#/definitions/uin !! 76 $ref: "/schemas/types.yaml#/definitions/uint32"
78 minimum: 0 77 minimum: 0
79 maximum: 0x1f 78 maximum: 0x1f
80 79
81 cdns,phy-input-delay-mmc-ddr: 80 cdns,phy-input-delay-mmc-ddr:
82 description: Value of the delay in the inp 81 description: Value of the delay in the input path for eMMC high-speed DDR timing
83 82
84 # PHY DLL clock delays: 83 # PHY DLL clock delays:
85 # Each delay property represents the fractio 84 # Each delay property represents the fraction of the clock period.
86 # The approximate delay value will be 85 # The approximate delay value will be
87 # (<delay property value>/128)*sdmclk_clock_ 86 # (<delay property value>/128)*sdmclk_clock_period.
88 $ref: /schemas/types.yaml#/definitions/uin !! 87 $ref: "/schemas/types.yaml#/definitions/uint32"
89 minimum: 0 88 minimum: 0
90 maximum: 0x1f 89 maximum: 0x1f
91 90
92 cdns,phy-dll-delay-sdclk: 91 cdns,phy-dll-delay-sdclk:
93 description: | 92 description: |
94 Value of the delay introduced on the sdc 93 Value of the delay introduced on the sdclk output for all modes except
95 HS200, HS400 and HS400_ES. 94 HS200, HS400 and HS400_ES.
96 $ref: /schemas/types.yaml#/definitions/uin !! 95 $ref: "/schemas/types.yaml#/definitions/uint32"
97 minimum: 0 96 minimum: 0
98 maximum: 0x7f 97 maximum: 0x7f
99 98
100 cdns,phy-dll-delay-sdclk-hsmmc: 99 cdns,phy-dll-delay-sdclk-hsmmc:
101 description: | 100 description: |
102 Value of the delay introduced on the sdc 101 Value of the delay introduced on the sdclk output for HS200, HS400 and
103 HS400_ES speed modes. 102 HS400_ES speed modes.
104 $ref: /schemas/types.yaml#/definitions/uin !! 103 $ref: "/schemas/types.yaml#/definitions/uint32"
105 minimum: 0 104 minimum: 0
106 maximum: 0x7f 105 maximum: 0x7f
107 106
108 cdns,phy-dll-delay-strobe: 107 cdns,phy-dll-delay-strobe:
109 description: | 108 description: |
110 Value of the delay introduced on the dat 109 Value of the delay introduced on the dat_strobe input used in
111 HS400 / HS400_ES speed modes. 110 HS400 / HS400_ES speed modes.
112 $ref: /schemas/types.yaml#/definitions/uin !! 111 $ref: "/schemas/types.yaml#/definitions/uint32"
113 minimum: 0 112 minimum: 0
114 maximum: 0x7f 113 maximum: 0x7f
115 114
116 required: 115 required:
117 - compatible 116 - compatible
118 - reg 117 - reg
119 - interrupts 118 - interrupts
120 - clocks 119 - clocks
121 <<
122 allOf: <<
123 - $ref: mmc-controller.yaml <<
124 - if: <<
125 properties: <<
126 compatible: <<
127 contains: <<
128 const: amd,pensando-elba-sd4hc <<
129 then: <<
130 properties: <<
131 reg: <<
132 items: <<
133 - description: Host controller reg <<
134 - description: Elba byte-lane enab <<
135 required: <<
136 - resets <<
137 else: <<
138 properties: <<
139 reg: <<
140 maxItems: 1 <<
141 120
142 unevaluatedProperties: false 121 unevaluatedProperties: false
143 122
144 examples: 123 examples:
145 - | 124 - |
146 emmc: mmc@5a000000 { 125 emmc: mmc@5a000000 {
147 compatible = "socionext,uniphier-sd4hc 126 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
148 reg = <0x5a000000 0x400>; 127 reg = <0x5a000000 0x400>;
149 interrupts = <0 78 4>; 128 interrupts = <0 78 4>;
150 clocks = <&clk 4>; 129 clocks = <&clk 4>;
151 bus-width = <8>; 130 bus-width = <8>;
152 mmc-ddr-1_8v; 131 mmc-ddr-1_8v;
153 mmc-hs200-1_8v; 132 mmc-hs200-1_8v;
154 mmc-hs400-1_8v; 133 mmc-hs400-1_8v;
155 cdns,phy-dll-delay-sdclk = <0>; 134 cdns,phy-dll-delay-sdclk = <0>;
156 }; 135 };
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