1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mmc/cdns,sd 4 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Cadence SD/SDIO/eMMC Host Controller (S 7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
8 8
9 maintainers: 9 maintainers:
10 - Masahiro Yamada <yamada.masahiro@socionext. 10 - Masahiro Yamada <yamada.masahiro@socionext.com>
>> 11 - Piotr Sroka <piotrs@cadence.com>
>> 12
>> 13 allOf:
>> 14 - $ref: mmc-controller.yaml
11 15
12 properties: 16 properties:
13 compatible: 17 compatible:
14 items: 18 items:
15 - enum: 19 - enum:
16 - amd,pensando-elba-sd4hc !! 20 - socionext,uniphier-sd4hc
17 - microchip,mpfs-sd4hc <<
18 - socionext,uniphier-sd4hc <<
19 - const: cdns,sd4hc 21 - const: cdns,sd4hc
20 22
21 reg: 23 reg:
22 minItems: 1 !! 24 maxItems: 1
23 maxItems: 2 <<
24 25
25 interrupts: 26 interrupts:
26 maxItems: 1 27 maxItems: 1
27 28
28 clocks: 29 clocks:
29 maxItems: 1 30 maxItems: 1
30 31
31 resets: <<
32 maxItems: 1 <<
33 <<
34 # PHY DLL input delays: 32 # PHY DLL input delays:
35 # They are used to delay the data valid wind 33 # They are used to delay the data valid window, and align the window to
36 # sampling clock. The delay starts from 5ns 34 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
37 # and it is increased by 2.5ns in each step. 35 # and it is increased by 2.5ns in each step.
38 36
39 cdns,phy-input-delay-sd-highspeed: 37 cdns,phy-input-delay-sd-highspeed:
40 description: Value of the delay in the inp 38 description: Value of the delay in the input path for SD high-speed timing
41 $ref: /schemas/types.yaml#/definitions/uin !! 39 allOf:
42 minimum: 0 !! 40 - $ref: "/schemas/types.yaml#/definitions/uint32"
43 maximum: 0x1f !! 41 - minimum: 0
>> 42 - maximum: 0x1f
44 43
45 cdns,phy-input-delay-legacy: 44 cdns,phy-input-delay-legacy:
46 description: Value of the delay in the inp 45 description: Value of the delay in the input path for legacy timing
47 $ref: /schemas/types.yaml#/definitions/uin !! 46 allOf:
48 minimum: 0 !! 47 - $ref: "/schemas/types.yaml#/definitions/uint32"
49 maximum: 0x1f !! 48 - minimum: 0
>> 49 - maximum: 0x1f
50 50
51 cdns,phy-input-delay-sd-uhs-sdr12: 51 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the inp 52 description: Value of the delay in the input path for SD UHS SDR12 timing
53 $ref: /schemas/types.yaml#/definitions/uin !! 53 allOf:
54 minimum: 0 !! 54 - $ref: "/schemas/types.yaml#/definitions/uint32"
55 maximum: 0x1f !! 55 - minimum: 0
>> 56 - maximum: 0x1f
56 57
57 cdns,phy-input-delay-sd-uhs-sdr25: 58 cdns,phy-input-delay-sd-uhs-sdr25:
58 description: Value of the delay in the inp 59 description: Value of the delay in the input path for SD UHS SDR25 timing
59 $ref: /schemas/types.yaml#/definitions/uin !! 60 allOf:
60 minimum: 0 !! 61 - $ref: "/schemas/types.yaml#/definitions/uint32"
61 maximum: 0x1f !! 62 - minimum: 0
>> 63 - maximum: 0x1f
62 64
63 cdns,phy-input-delay-sd-uhs-sdr50: 65 cdns,phy-input-delay-sd-uhs-sdr50:
64 description: Value of the delay in the inp 66 description: Value of the delay in the input path for SD UHS SDR50 timing
65 $ref: /schemas/types.yaml#/definitions/uin !! 67 allOf:
66 minimum: 0 !! 68 - $ref: "/schemas/types.yaml#/definitions/uint32"
67 maximum: 0x1f !! 69 - minimum: 0
>> 70 - maximum: 0x1f
68 71
69 cdns,phy-input-delay-sd-uhs-ddr50: 72 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the inp 73 description: Value of the delay in the input path for SD UHS DDR50 timing
71 $ref: /schemas/types.yaml#/definitions/uin !! 74 allOf:
72 minimum: 0 !! 75 - $ref: "/schemas/types.yaml#/definitions/uint32"
73 maximum: 0x1f !! 76 - minimum: 0
>> 77 - maximum: 0x1f
74 78
75 cdns,phy-input-delay-mmc-highspeed: 79 cdns,phy-input-delay-mmc-highspeed:
76 description: Value of the delay in the inp 80 description: Value of the delay in the input path for MMC high-speed timing
77 $ref: /schemas/types.yaml#/definitions/uin !! 81 allOf:
78 minimum: 0 !! 82 - $ref: "/schemas/types.yaml#/definitions/uint32"
79 maximum: 0x1f !! 83 - minimum: 0
>> 84 - maximum: 0x1f
80 85
81 cdns,phy-input-delay-mmc-ddr: 86 cdns,phy-input-delay-mmc-ddr:
82 description: Value of the delay in the inp 87 description: Value of the delay in the input path for eMMC high-speed DDR timing
>> 88 allOf:
>> 89 - $ref: "/schemas/types.yaml#/definitions/uint32"
>> 90 - minimum: 0
>> 91 - maximum: 0x1f
83 92
84 # PHY DLL clock delays: 93 # PHY DLL clock delays:
85 # Each delay property represents the fractio 94 # Each delay property represents the fraction of the clock period.
86 # The approximate delay value will be 95 # The approximate delay value will be
87 # (<delay property value>/128)*sdmclk_clock_ 96 # (<delay property value>/128)*sdmclk_clock_period.
88 $ref: /schemas/types.yaml#/definitions/uin <<
89 minimum: 0 <<
90 maximum: 0x1f <<
91 97
92 cdns,phy-dll-delay-sdclk: 98 cdns,phy-dll-delay-sdclk:
93 description: | 99 description: |
94 Value of the delay introduced on the sdc 100 Value of the delay introduced on the sdclk output for all modes except
95 HS200, HS400 and HS400_ES. 101 HS200, HS400 and HS400_ES.
96 $ref: /schemas/types.yaml#/definitions/uin !! 102 allOf:
97 minimum: 0 !! 103 - $ref: "/schemas/types.yaml#/definitions/uint32"
98 maximum: 0x7f !! 104 - minimum: 0
>> 105 - maximum: 0x7f
99 106
100 cdns,phy-dll-delay-sdclk-hsmmc: 107 cdns,phy-dll-delay-sdclk-hsmmc:
101 description: | 108 description: |
102 Value of the delay introduced on the sdc 109 Value of the delay introduced on the sdclk output for HS200, HS400 and
103 HS400_ES speed modes. 110 HS400_ES speed modes.
104 $ref: /schemas/types.yaml#/definitions/uin !! 111 allOf:
105 minimum: 0 !! 112 - $ref: "/schemas/types.yaml#/definitions/uint32"
106 maximum: 0x7f !! 113 - minimum: 0
>> 114 - maximum: 0x7f
107 115
108 cdns,phy-dll-delay-strobe: 116 cdns,phy-dll-delay-strobe:
109 description: | 117 description: |
110 Value of the delay introduced on the dat 118 Value of the delay introduced on the dat_strobe input used in
111 HS400 / HS400_ES speed modes. 119 HS400 / HS400_ES speed modes.
112 $ref: /schemas/types.yaml#/definitions/uin !! 120 allOf:
113 minimum: 0 !! 121 - $ref: "/schemas/types.yaml#/definitions/uint32"
114 maximum: 0x7f !! 122 - minimum: 0
>> 123 - maximum: 0x7f
115 124
116 required: 125 required:
117 - compatible 126 - compatible
118 - reg 127 - reg
119 - interrupts 128 - interrupts
120 - clocks 129 - clocks
121 <<
122 allOf: <<
123 - $ref: mmc-controller.yaml <<
124 - if: <<
125 properties: <<
126 compatible: <<
127 contains: <<
128 const: amd,pensando-elba-sd4hc <<
129 then: <<
130 properties: <<
131 reg: <<
132 items: <<
133 - description: Host controller reg <<
134 - description: Elba byte-lane enab <<
135 required: <<
136 - resets <<
137 else: <<
138 properties: <<
139 reg: <<
140 maxItems: 1 <<
141 <<
142 unevaluatedProperties: false <<
143 130
144 examples: 131 examples:
145 - | 132 - |
146 emmc: mmc@5a000000 { 133 emmc: mmc@5a000000 {
147 compatible = "socionext,uniphier-sd4hc 134 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
148 reg = <0x5a000000 0x400>; 135 reg = <0x5a000000 0x400>;
149 interrupts = <0 78 4>; 136 interrupts = <0 78 4>;
150 clocks = <&clk 4>; 137 clocks = <&clk 4>;
151 bus-width = <8>; 138 bus-width = <8>;
152 mmc-ddr-1_8v; 139 mmc-ddr-1_8v;
153 mmc-hs200-1_8v; 140 mmc-hs200-1_8v;
154 mmc-hs400-1_8v; 141 mmc-hs400-1_8v;
155 cdns,phy-dll-delay-sdclk = <0>; 142 cdns,phy-dll-delay-sdclk = <0>;
156 }; 143 };
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