1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung 4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: 7 title:
8 Samsung Exynos SoC specific extensions to th 8 Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
9 Storage Host Controller 9 Storage Host Controller
10 10
11 maintainers: 11 maintainers:
12 - Jaehoon Chung <jh80.chung@samsung.com> 12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org> 13 - Krzysztof Kozlowski <krzk@kernel.org>
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 oneOf: 17 oneOf:
18 - enum: 18 - enum:
19 - axis,artpec8-dw-mshc 19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc 20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc 21 - samsung,exynos4412-dw-mshc
22 - samsung,exynos5250-dw-mshc 22 - samsung,exynos5250-dw-mshc
23 - samsung,exynos5420-dw-mshc 23 - samsung,exynos5420-dw-mshc
24 - samsung,exynos5420-dw-mshc-smu 24 - samsung,exynos5420-dw-mshc-smu
25 - samsung,exynos7-dw-mshc 25 - samsung,exynos7-dw-mshc
26 - samsung,exynos7-dw-mshc-smu 26 - samsung,exynos7-dw-mshc-smu
27 - items: 27 - items:
28 - enum: 28 - enum:
29 - samsung,exynos5433-dw-mshc-smu 29 - samsung,exynos5433-dw-mshc-smu
30 - samsung,exynos7885-dw-mshc-smu 30 - samsung,exynos7885-dw-mshc-smu
31 - samsung,exynos850-dw-mshc-smu 31 - samsung,exynos850-dw-mshc-smu
32 - const: samsung,exynos7-dw-mshc-smu 32 - const: samsung,exynos7-dw-mshc-smu
33 33
34 reg: 34 reg:
35 maxItems: 1 35 maxItems: 1
36 36
37 interrupts: 37 interrupts:
38 maxItems: 1 38 maxItems: 1
39 39
40 clocks: 40 clocks:
41 maxItems: 2 41 maxItems: 2
42 description: 42 description:
43 Handle to "biu" and "ciu" clocks for the 43 Handle to "biu" and "ciu" clocks for the
44 bus interface unit clock and the card in 44 bus interface unit clock and the card interface unit clock.
45 45
46 clock-names: 46 clock-names:
47 items: 47 items:
48 - const: biu 48 - const: biu
49 - const: ciu 49 - const: ciu
50 50
51 samsung,dw-mshc-ciu-div: 51 samsung,dw-mshc-ciu-div:
52 $ref: /schemas/types.yaml#/definitions/uin 52 $ref: /schemas/types.yaml#/definitions/uint32
53 minimum: 0 53 minimum: 0
54 maximum: 7 54 maximum: 7
55 description: 55 description:
56 The divider value for the card interface 56 The divider value for the card interface unit (ciu) clock.
57 57
58 samsung,dw-mshc-ddr-timing: 58 samsung,dw-mshc-ddr-timing:
59 $ref: /schemas/types.yaml#/definitions/uin 59 $ref: /schemas/types.yaml#/definitions/uint32-array
60 items: 60 items:
61 - description: CIU clock phase shift val 61 - description: CIU clock phase shift value for tx mode
62 minimum: 0 62 minimum: 0
63 maximum: 7 63 maximum: 7
64 - description: CIU clock phase shift val 64 - description: CIU clock phase shift value for rx mode
65 minimum: 0 65 minimum: 0
66 maximum: 7 66 maximum: 7
67 description: 67 description:
68 The value of CUI clock phase shift value 68 The value of CUI clock phase shift value in transmit mode and CIU clock
69 phase shift value in receive mode for do 69 phase shift value in receive mode for double data rate mode operation.
70 See also samsung,dw-mshc-hs400-timing pr 70 See also samsung,dw-mshc-hs400-timing property.
71 71
72 samsung,dw-mshc-hs400-timing: 72 samsung,dw-mshc-hs400-timing:
73 $ref: /schemas/types.yaml#/definitions/uin 73 $ref: /schemas/types.yaml#/definitions/uint32-array
74 items: 74 items:
75 - description: CIU clock phase shift val 75 - description: CIU clock phase shift value for tx mode
76 minimum: 0 76 minimum: 0
77 maximum: 7 77 maximum: 7
78 - description: CIU clock phase shift val 78 - description: CIU clock phase shift value for rx mode
79 minimum: 0 79 minimum: 0
80 maximum: 7 80 maximum: 7
81 description: | 81 description: |
82 The value of CIU TX and RX clock phase s 82 The value of CIU TX and RX clock phase shift value for HS400 mode
83 operation. 83 operation.
84 Valid values for SDR and DDR CIU clock t 84 Valid values for SDR and DDR CIU clock timing::
85 - valid value for tx phase shift and r 85 - valid value for tx phase shift and rx phase shift is 0 to 7.
86 - when CIU clock divider value is set 86 - when CIU clock divider value is set to 3, all possible 8 phase shift
87 values can be used. 87 values can be used.
88 - if CIU clock divider value is 0 (tha 88 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
89 phase shift clocks should be 0. 89 phase shift clocks should be 0.
90 If missing, values from samsung,dw-mshc- 90 If missing, values from samsung,dw-mshc-ddr-timing property are used.
91 91
92 samsung,dw-mshc-sdr-timing: 92 samsung,dw-mshc-sdr-timing:
93 $ref: /schemas/types.yaml#/definitions/uin 93 $ref: /schemas/types.yaml#/definitions/uint32-array
94 items: 94 items:
95 - description: CIU clock phase shift val 95 - description: CIU clock phase shift value for tx mode
96 minimum: 0 96 minimum: 0
97 maximum: 7 97 maximum: 7
98 - description: CIU clock phase shift val 98 - description: CIU clock phase shift value for rx mode
99 minimum: 0 99 minimum: 0
100 maximum: 7 100 maximum: 7
101 description: 101 description:
102 The value of CIU clock phase shift value 102 The value of CIU clock phase shift value in transmit mode and CIU clock
103 phase shift value in receive mode for si 103 phase shift value in receive mode for single data rate mode operation.
104 See also samsung,dw-mshc-hs400-timing pr 104 See also samsung,dw-mshc-hs400-timing property.
105 105
106 samsung,read-strobe-delay: 106 samsung,read-strobe-delay:
107 $ref: /schemas/types.yaml#/definitions/uin 107 $ref: /schemas/types.yaml#/definitions/uint32
108 description: 108 description:
109 RCLK (Data strobe) delay to control HS40 109 RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
110 line in Read path). If missing, default 110 line in Read path). If missing, default from hardware is used.
111 111
112 required: 112 required:
113 - compatible 113 - compatible
114 - reg 114 - reg
115 - interrupts 115 - interrupts
116 - clocks 116 - clocks
117 - clock-names 117 - clock-names
118 - samsung,dw-mshc-ddr-timing 118 - samsung,dw-mshc-ddr-timing
119 - samsung,dw-mshc-sdr-timing 119 - samsung,dw-mshc-sdr-timing
120 120
121 allOf: 121 allOf:
122 - $ref: synopsys-dw-mshc-common.yaml# 122 - $ref: synopsys-dw-mshc-common.yaml#
123 - if: 123 - if:
124 properties: 124 properties:
125 compatible: 125 compatible:
126 contains: 126 contains:
127 enum: 127 enum:
128 - samsung,exynos5250-dw-mshc 128 - samsung,exynos5250-dw-mshc
129 - samsung,exynos5420-dw-mshc 129 - samsung,exynos5420-dw-mshc
130 - samsung,exynos7-dw-mshc 130 - samsung,exynos7-dw-mshc
131 - samsung,exynos7-dw-mshc-smu 131 - samsung,exynos7-dw-mshc-smu
132 - axis,artpec8-dw-mshc 132 - axis,artpec8-dw-mshc
133 then: 133 then:
134 required: 134 required:
135 - samsung,dw-mshc-ciu-div 135 - samsung,dw-mshc-ciu-div
136 136
137 unevaluatedProperties: false 137 unevaluatedProperties: false
138 138
139 examples: 139 examples:
140 - | 140 - |
141 #include <dt-bindings/clock/exynos5420.h> 141 #include <dt-bindings/clock/exynos5420.h>
142 #include <dt-bindings/interrupt-controller 142 #include <dt-bindings/interrupt-controller/arm-gic.h>
143 143
144 mmc@12220000 { 144 mmc@12220000 {
145 compatible = "samsung,exynos5420-dw-ms 145 compatible = "samsung,exynos5420-dw-mshc";
146 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVE 146 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
147 #address-cells = <1>; 147 #address-cells = <1>;
148 #size-cells = <0>; 148 #size-cells = <0>;
149 reg = <0x12220000 0x1000>; 149 reg = <0x12220000 0x1000>;
150 clocks = <&clock CLK_MMC2>, <&clock CL 150 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
151 clock-names = "biu", "ciu"; 151 clock-names = "biu", "ciu";
152 fifo-depth = <0x40>; 152 fifo-depth = <0x40>;
153 card-detect-delay = <200>; 153 card-detect-delay = <200>;
154 samsung,dw-mshc-ciu-div = <3>; 154 samsung,dw-mshc-ciu-div = <3>;
155 samsung,dw-mshc-sdr-timing = <0 4>; 155 samsung,dw-mshc-sdr-timing = <0 4>;
156 samsung,dw-mshc-ddr-timing = <0 2>; 156 samsung,dw-mshc-ddr-timing = <0 2>;
157 pinctrl-names = "default"; 157 pinctrl-names = "default";
158 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd 158 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
159 bus-width = <4>; 159 bus-width = <4>;
160 cap-sd-highspeed; 160 cap-sd-highspeed;
161 max-frequency = <200000000>; 161 max-frequency = <200000000>;
162 vmmc-supply = <&ldo19_reg>; 162 vmmc-supply = <&ldo19_reg>;
163 vqmmc-supply = <&ldo13_reg>; 163 vqmmc-supply = <&ldo13_reg>;
164 sd-uhs-sdr50; 164 sd-uhs-sdr50;
165 sd-uhs-sdr104; 165 sd-uhs-sdr104;
166 sd-uhs-ddr50; 166 sd-uhs-ddr50;
167 }; 167 };
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