1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Cl 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sd 4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Spreadtrum SDHCI controller 7 title: Spreadtrum SDHCI controller
8 8
9 maintainers: 9 maintainers:
10 - Orson Zhai <orsonzhai@gmail.com> 10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com> 11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com> 12 - Chunyan Zhang <zhang.lyra@gmail.com>
13 13
14 properties: 14 properties:
15 compatible: 15 compatible:
16 const: sprd,sdhci-r11 16 const: sprd,sdhci-r11
17 17
18 reg: 18 reg:
19 maxItems: 1 19 maxItems: 1
20 20
21 interrupts: 21 interrupts:
22 maxItems: 1 22 maxItems: 1
23 23
24 clocks: 24 clocks:
25 minItems: 2 25 minItems: 2
26 items: 26 items:
27 - description: SDIO source clock 27 - description: SDIO source clock
28 - description: gate clock for enabling/d 28 - description: gate clock for enabling/disabling the device
29 - description: gate clock controlling th 29 - description: gate clock controlling the device for some special platforms (optional)
30 30
31 clock-names: 31 clock-names:
32 minItems: 2 32 minItems: 2
33 items: 33 items:
34 - const: sdio 34 - const: sdio
35 - const: enable 35 - const: enable
36 - const: 2x_enable 36 - const: 2x_enable
37 37
38 pinctrl-0: 38 pinctrl-0:
39 description: default/high speed pin contro 39 description: default/high speed pin control
40 maxItems: 1 40 maxItems: 1
41 41
42 pinctrl-1: 42 pinctrl-1:
43 description: UHS mode pin control 43 description: UHS mode pin control
44 maxItems: 1 44 maxItems: 1
45 45
46 pinctrl-names: 46 pinctrl-names:
47 minItems: 1 47 minItems: 1
48 items: 48 items:
49 - const: default 49 - const: default
50 - const: state_uhs 50 - const: state_uhs
51 51
52 patternProperties: 52 patternProperties:
53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspee 53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$":
54 $ref: /schemas/types.yaml#/definitions/uin 54 $ref: /schemas/types.yaml#/definitions/uint32-array
55 items: 55 items:
56 - description: clock data write line del 56 - description: clock data write line delay value
57 - description: clock read command line d 57 - description: clock read command line delay value
58 - description: clock read data positive 58 - description: clock read data positive edge delay value
59 - description: clock read data negative 59 - description: clock read data negative edge delay value
60 description: 60 description:
61 PHY DLL delays are used to delay the dat 61 PHY DLL delays are used to delay the data valid window, and align
62 the window to the sampling clock. Each c 62 the window to the sampling clock. Each cell's delay value unit is
63 cycle of the PHY clock. 63 cycle of the PHY clock.
64 64
65 required: 65 required:
66 - compatible 66 - compatible
67 - reg 67 - reg
68 - interrupts 68 - interrupts
69 - clocks 69 - clocks
70 - clock-names 70 - clock-names
71 71
72 allOf: 72 allOf:
73 - $ref: sdhci-common.yaml# 73 - $ref: sdhci-common.yaml#
74 74
75 unevaluatedProperties: false 75 unevaluatedProperties: false
76 76
77 examples: 77 examples:
78 - | 78 - |
79 #include <dt-bindings/clock/sprd,sc9860-cl 79 #include <dt-bindings/clock/sprd,sc9860-clk.h>
80 #include <dt-bindings/interrupt-controller 80 #include <dt-bindings/interrupt-controller/arm-gic.h>
81 #include <dt-bindings/interrupt-controller 81 #include <dt-bindings/interrupt-controller/irq.h>
82 82
83 mmc@50430000 { 83 mmc@50430000 {
84 compatible = "sprd,sdhci-r11"; 84 compatible = "sprd,sdhci-r11";
85 reg = <0x50430000 0x1000>; 85 reg = <0x50430000 0x1000>;
86 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_ 86 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
87 87
88 clocks = <&aon_prediv CLK_EMMC_2X>, 88 clocks = <&aon_prediv CLK_EMMC_2X>,
89 <&apahb_gate CLK_EMMC_EB>, 89 <&apahb_gate CLK_EMMC_EB>,
90 <&aon_gate CLK_EMMC_2X_EN>; 90 <&aon_gate CLK_EMMC_2X_EN>;
91 clock-names = "sdio", "enable", "2x_enab 91 clock-names = "sdio", "enable", "2x_enable";
92 92
93 pinctrl-0 = <&sd0_pins_default>; 93 pinctrl-0 = <&sd0_pins_default>;
94 pinctrl-1 = <&sd0_pins_uhs>; 94 pinctrl-1 = <&sd0_pins_uhs>;
95 pinctrl-names = "default", "state_uhs"; 95 pinctrl-names = "default", "state_uhs";
96 96
97 bus-width = <8>; 97 bus-width = <8>;
98 cap-mmc-hw-reset; 98 cap-mmc-hw-reset;
99 mmc-hs400-enhanced-strobe; 99 mmc-hs400-enhanced-strobe;
100 mmc-hs400-1_8v; 100 mmc-hs400-1_8v;
101 mmc-hs200-1_8v; 101 mmc-hs200-1_8v;
102 mmc-ddr-1_8v; 102 mmc-ddr-1_8v;
103 non-removable; 103 non-removable;
104 no-sdio; 104 no-sdio;
105 no-sd; 105 no-sd;
106 106
107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x 107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
108 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8 108 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
109 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x 109 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
110 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 110 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;
111 }; 111 };
112 ... 112 ...
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