1 Atmel NAND flash controller bindings 1 Atmel NAND flash controller bindings
2 2
3 The NAND flash controller node should be defin 3 The NAND flash controller node should be defined under the EBI bus (see
4 Documentation/devicetree/bindings/memory-contr 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
5 One or several NAND devices can be defined und 5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an E 6 The NAND controller might be connected to an ECC engine.
7 7
8 * NAND controller bindings: 8 * NAND controller bindings:
9 9
10 Required properties: 10 Required properties:
11 - compatible: should be one of the following 11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller" 12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller" 13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller" 14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller" 15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller" 16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller" 17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI 18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2. 19 - #address-cells: should be set to 2.
20 - #size-cells: should be set to 1. 20 - #size-cells: should be set to 1.
21 - atmel,nfc-io: phandle to the NFC IO block. O 21 - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
22 controllers. 22 controllers.
23 - atmel,nfc-sram: phandle to the NFC SRAM bloc 23 - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
24 controllers. 24 controllers.
25 25
26 Optional properties: 26 Optional properties:
27 - ecc-engine: phandle to the PMECC block. Only 27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
28 a PMECC engine. 28 a PMECC engine.
29 29
30 * NAND device/chip bindings: 30 * NAND device/chip bindings:
31 31
32 Required properties: 32 Required properties:
33 - reg: describes the CS lines assigned to the 33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
34 exposes multiple CS lines (multi-dies c 34 exposes multiple CS lines (multi-dies chips), your reg property will
35 contain X tuples of 3 entries. 35 contain X tuples of 3 entries.
36 1st entry: the CS line this NAND chip i 36 1st entry: the CS line this NAND chip is connected to
37 2nd entry: the base offset of the memor 37 2nd entry: the base offset of the memory region assigned to this
38 device (always 0) 38 device (always 0)
39 3rd entry: the memory region size (alwa 39 3rd entry: the memory region size (always 0x800000)
40 40
41 Optional properties: 41 Optional properties:
42 - rb-gpios: the GPIO(s) used to check the Read 42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
43 - cs-gpios: the GPIO(s) used to control the CS 43 - cs-gpios: the GPIO(s) used to control the CS line.
44 - det-gpios: the GPIO used to detect if a Smar 44 - det-gpios: the GPIO used to detect if a Smartmedia Card is present.
45 - atmel,rb: an integer identifying the native 45 - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
46 on sama5 SoCs. 46 on sama5 SoCs.
47 47
48 All generic properties are described in the ge 48 All generic properties are described in the generic yaml files under
49 Documentation/devicetree/bindings/mtd/. 49 Documentation/devicetree/bindings/mtd/.
50 50
51 * ECC engine (PMECC) bindings: 51 * ECC engine (PMECC) bindings:
52 52
53 Required properties: 53 Required properties:
54 - compatible: should be one of the following 54 - compatible: should be one of the following
55 "atmel,at91sam9g45-pmecc" 55 "atmel,at91sam9g45-pmecc"
56 "atmel,sama5d4-pmecc" 56 "atmel,sama5d4-pmecc"
57 "atmel,sama5d2-pmecc" 57 "atmel,sama5d2-pmecc"
58 "microchip,sam9x60-pmecc" 58 "microchip,sam9x60-pmecc"
59 "microchip,sam9x7-pmecc", "atmel,at91s 59 "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
60 - reg: should contain 2 register ranges. The f 60 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
61 block, and the second one to the PMECC_ 61 block, and the second one to the PMECC_ERRLOC block.
62 62
>> 63 * SAMA5 NFC I/O bindings:
>> 64
>> 65 SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
>> 66 operations. This interface to this logic is placed in a separate I/O range and
>> 67 should thus have its own DT node.
>> 68
>> 69 - compatible: should be "atmel,sama5d3-nfc-io", "syscon".
>> 70 - reg: should contain the I/O range used to interact with the NFC logic.
>> 71
63 Example: 72 Example:
64 73
65 nfc_io: nfc-io@70000000 { 74 nfc_io: nfc-io@70000000 {
66 compatible = "atmel,sama5d3-nf 75 compatible = "atmel,sama5d3-nfc-io", "syscon";
67 reg = <0x70000000 0x8000000>; 76 reg = <0x70000000 0x8000000>;
68 }; 77 };
69 78
70 pmecc: ecc-engine@ffffc070 { 79 pmecc: ecc-engine@ffffc070 {
71 compatible = "atmel,at91sam9g4 80 compatible = "atmel,at91sam9g45-pmecc";
72 reg = <0xffffc070 0x490>, 81 reg = <0xffffc070 0x490>,
73 <0xffffc500 0x100>; 82 <0xffffc500 0x100>;
74 }; 83 };
75 84
76 ebi: ebi@10000000 { 85 ebi: ebi@10000000 {
77 compatible = "atmel,sama5d3-eb 86 compatible = "atmel,sama5d3-ebi";
78 #address-cells = <2>; 87 #address-cells = <2>;
79 #size-cells = <1>; 88 #size-cells = <1>;
80 atmel,smc = <&hsmc>; 89 atmel,smc = <&hsmc>;
81 reg = <0x10000000 0x10000000 90 reg = <0x10000000 0x10000000
82 0x40000000 0x30000000>; 91 0x40000000 0x30000000>;
83 ranges = <0x0 0x0 0x10000000 0 92 ranges = <0x0 0x0 0x10000000 0x10000000
84 0x1 0x0 0x40000000 0 93 0x1 0x0 0x40000000 0x10000000
85 0x2 0x0 0x50000000 0 94 0x2 0x0 0x50000000 0x10000000
86 0x3 0x0 0x60000000 0 95 0x3 0x0 0x60000000 0x10000000>;
87 clocks = <&mck>; 96 clocks = <&mck>;
88 97
89 nand_controller: nand-controll 98 nand_controller: nand-controller {
90 compatible = "atmel,sa 99 compatible = "atmel,sama5d3-nand-controller";
91 atmel,nfc-sram = <&nfc 100 atmel,nfc-sram = <&nfc_sram>;
92 atmel,nfc-io = <&nfc_i 101 atmel,nfc-io = <&nfc_io>;
93 ecc-engine = <&pmecc>; 102 ecc-engine = <&pmecc>;
94 #address-cells = <2>; 103 #address-cells = <2>;
95 #size-cells = <1>; 104 #size-cells = <1>;
96 ranges; 105 ranges;
97 106
98 nand@3 { 107 nand@3 {
99 reg = <0x3 0x0 108 reg = <0x3 0x0 0x800000>;
100 atmel,rb = <0> 109 atmel,rb = <0>;
101 110
102 /* 111 /*
103 * Put generic 112 * Put generic NAND/MTD properties and
104 * subnodes he 113 * subnodes here.
105 */ 114 */
106 }; 115 };
107 }; 116 };
108 }; 117 };
109 118
110 ---------------------------------------------- 119 -----------------------------------------------------------------------
111 120
112 Deprecated bindings (should not be used in new 121 Deprecated bindings (should not be used in new device trees):
113 122
114 Required properties: 123 Required properties:
115 - compatible: The possible values are: 124 - compatible: The possible values are:
116 "atmel,at91rm9200-nand" 125 "atmel,at91rm9200-nand"
117 "atmel,sama5d2-nand" 126 "atmel,sama5d2-nand"
118 "atmel,sama5d4-nand" 127 "atmel,sama5d4-nand"
119 - reg : should specify localbus address and si 128 - reg : should specify localbus address and size used for the chip,
120 and hardware ECC controller if availab 129 and hardware ECC controller if available.
121 If the hardware ECC is PMECC, it shoul 130 If the hardware ECC is PMECC, it should contain address and size for
122 PMECC and PMECC Error Location control 131 PMECC and PMECC Error Location controller.
123 The PMECC lookup table address and siz 132 The PMECC lookup table address and size in ROM is optional. If not
124 specified, driver will build it in run 133 specified, driver will build it in runtime.
125 - atmel,nand-addr-offset : offset for the addr 134 - atmel,nand-addr-offset : offset for the address latch.
126 - atmel,nand-cmd-offset : offset for the comma 135 - atmel,nand-cmd-offset : offset for the command latch.
127 - #address-cells, #size-cells : Must be presen 136 - #address-cells, #size-cells : Must be present if the device has sub-nodes
128 representing partitions. 137 representing partitions.
129 138
130 - gpios : specifies the gpio pins to control t 139 - gpios : specifies the gpio pins to control the NAND device. detect is an
131 optional gpio and may be set to 0 if not pre 140 optional gpio and may be set to 0 if not present.
132 141
133 Optional properties: 142 Optional properties:
134 - atmel,nand-has-dma : boolean to support dma 143 - atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
135 - nand-ecc-mode : String, operation mode of th 144 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
136 Supported values are: "none", "soft", "hw", 145 Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
137 "soft_bch". 146 "soft_bch".
138 - atmel,has-pmecc : boolean to enable Programm 147 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
139 capable of BCH encoding and decoding, on dev 148 capable of BCH encoding and decoding, on devices where it is present.
140 - atmel,pmecc-cap : error correct capability f 149 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
141 Controller. Supported values are: 2, 4, 8, 1 150 Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
142 is "atmel,sama5d2-nand", 32 is also valid. 151 is "atmel,sama5d2-nand", 32 is also valid.
143 - atmel,pmecc-sector-size : sector size for EC 152 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
144 are: 512, 1024. 153 are: 512, 1024.
145 - atmel,pmecc-lookup-table-offset : includes t 154 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
146 for different sector size. First one is for 155 for different sector size. First one is for sector size 512, the next is for
147 sector size 1024. If not specified, driver w 156 sector size 1024. If not specified, driver will build the table in runtime.
148 - nand-bus-width : 8 or 16 bus width if not pr 157 - nand-bus-width : 8 or 16 bus width if not present 8
149 - nand-on-flash-bbt: boolean to enable on flas 158 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
150 159
151 Nand Flash Controller(NFC) is an optional sub- 160 Nand Flash Controller(NFC) is an optional sub-node
152 Required properties: 161 Required properties:
153 - compatible : "atmel,sama5d3-nfc". 162 - compatible : "atmel,sama5d3-nfc".
154 - reg : should specify the address and size us 163 - reg : should specify the address and size used for NFC command registers,
155 NFC registers and NFC SRAM. NFC SRAM a 164 NFC registers and NFC SRAM. NFC SRAM address and size can be absent
156 if don't want to use it. 165 if don't want to use it.
157 - clocks: phandle to the peripheral clock 166 - clocks: phandle to the peripheral clock
158 Optional properties: 167 Optional properties:
159 - atmel,write-by-sram: boolean to enable NFC w 168 - atmel,write-by-sram: boolean to enable NFC write by SRAM.
160 169
161 Examples: 170 Examples:
162 nand0: nand@40000000,0 { 171 nand0: nand@40000000,0 {
163 compatible = "atmel,at91rm9200-nand"; 172 compatible = "atmel,at91rm9200-nand";
164 #address-cells = <1>; 173 #address-cells = <1>;
165 #size-cells = <1>; 174 #size-cells = <1>;
166 reg = <0x40000000 0x10000000 175 reg = <0x40000000 0x10000000
167 0xffffe800 0x200 176 0xffffe800 0x200
168 >; 177 >;
169 atmel,nand-addr-offset = <21>; /* ale 178 atmel,nand-addr-offset = <21>; /* ale */
170 atmel,nand-cmd-offset = <22>; /* cle 179 atmel,nand-cmd-offset = <22>; /* cle */
171 nand-on-flash-bbt; 180 nand-on-flash-bbt;
172 nand-ecc-mode = "soft"; 181 nand-ecc-mode = "soft";
173 gpios = <&pioC 13 0 /* rdy */ 182 gpios = <&pioC 13 0 /* rdy */
174 &pioC 14 0 /* nce */ 183 &pioC 14 0 /* nce */
175 0 /* cd */ 184 0 /* cd */
176 >; 185 >;
177 partition@0 { 186 partition@0 {
178 ... 187 ...
179 }; 188 };
180 }; 189 };
181 190
182 /* for PMECC supported chips */ 191 /* for PMECC supported chips */
183 nand0: nand@40000000 { 192 nand0: nand@40000000 {
184 compatible = "atmel,at91rm9200-nand"; 193 compatible = "atmel,at91rm9200-nand";
185 #address-cells = <1>; 194 #address-cells = <1>;
186 #size-cells = <1>; 195 #size-cells = <1>;
187 reg = < 0x40000000 0x10000000 /* bus 196 reg = < 0x40000000 0x10000000 /* bus addr & size */
188 0xffffe000 0x00000600 /* PME 197 0xffffe000 0x00000600 /* PMECC addr & size */
189 0xffffe600 0x00000200 /* PME 198 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
190 0x00100000 0x00100000 /* ROM 199 0x00100000 0x00100000 /* ROM addr & size */
191 >; 200 >;
192 atmel,nand-addr-offset = <21>; /* ale 201 atmel,nand-addr-offset = <21>; /* ale */
193 atmel,nand-cmd-offset = <22>; /* cle 202 atmel,nand-cmd-offset = <22>; /* cle */
194 nand-on-flash-bbt; 203 nand-on-flash-bbt;
195 nand-ecc-mode = "hw"; 204 nand-ecc-mode = "hw";
196 atmel,has-pmecc; /* enable PMEC 205 atmel,has-pmecc; /* enable PMECC */
197 atmel,pmecc-cap = <2>; 206 atmel,pmecc-cap = <2>;
198 atmel,pmecc-sector-size = <512>; 207 atmel,pmecc-sector-size = <512>;
199 atmel,pmecc-lookup-table-offset = <0x8 208 atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
200 gpios = <&pioD 5 0 /* rdy */ 209 gpios = <&pioD 5 0 /* rdy */
201 &pioD 4 0 /* nce */ 210 &pioD 4 0 /* nce */
202 0 /* cd */ 211 0 /* cd */
203 >; 212 >;
204 partition@0 { 213 partition@0 {
205 ... 214 ...
206 }; 215 };
207 }; 216 };
208 217
209 /* for NFC supported chips */ 218 /* for NFC supported chips */
210 nand0: nand@40000000 { 219 nand0: nand@40000000 {
211 compatible = "atmel,at91rm9200-nand"; 220 compatible = "atmel,at91rm9200-nand";
212 #address-cells = <1>; 221 #address-cells = <1>;
213 #size-cells = <1>; 222 #size-cells = <1>;
214 ranges; 223 ranges;
215 ... 224 ...
216 nfc@70000000 { 225 nfc@70000000 {
217 compatible = "atmel,sama5d3-nf 226 compatible = "atmel,sama5d3-nfc";
218 #address-cells = <1>; 227 #address-cells = <1>;
219 #size-cells = <1>; 228 #size-cells = <1>;
220 clocks = <&hsmc_clk> 229 clocks = <&hsmc_clk>
221 reg = < 230 reg = <
222 0x70000000 0x10000000 231 0x70000000 0x10000000 /* NFC Command Registers */
223 0xffffc000 0x00000070 232 0xffffc000 0x00000070 /* NFC HSMC regs */
224 0x00200000 0x00100000 233 0x00200000 0x00100000 /* NFC SRAM banks */
225 >; 234 >;
226 }; 235 };
227 }; 236 };
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