1 * Cadence NAND controller
2
3 Required properties:
4 - compatible : "cdns,hp-nfc"
5 - reg : Contains two entries, each of which
6 physical address and length. The fir
7 length of the controller register se
8 address and length of the Slave DMA
9 - reg-names: should contain "reg" and "sdma"
10 - #address-cells: should be 1. The cell enco
11 - #size-cells : should be 0.
12 - interrupts : The interrupt number.
13 - clocks: phandle of the controller core clo
14
15 Optional properties:
16 - dmas: shall reference DMA channel associat
17 - cdns,board-delay-ps : Estimated Board dela
18 round trip delay for the signals and is us
19 associated with data read capture. The exa
20 the following:
21 board delay = RE#PAD delay + PCB trace to
22 + DQ PAD delay
23
24 Child nodes represent the available NAND chips
25
26 Required properties of NAND chips:
27 - reg: shall contain the native Chip Select
28 the cadence nand flash controller
29
30 See Documentation/devicetree/bindings/mtd/nand
31 generic bindings.
32
33 Example:
34
35 nand_controller: nand-controller@60000000 {
36 compatible = "cdns,hp-nfc";
37 #address-cells = <1>;
38 #size-cells = <0>;
39 reg = <0x60000000 0x10000>, <0x80000
40 reg-names = "reg", "sdma";
41 clocks = <&nf_clk>;
42 cdns,board-delay-ps = <4830>;
43 interrupts = <2 0>;
44 nand@0 {
45 reg = <0>;
46 label = "nand-1";
47 };
48 nand@1 {
49 reg = <1>;
50 label = "nand-2";
51 };
52
53 };
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