1 Freescale Localbus UPM programmed to work with 1 Freescale Localbus UPM programmed to work with NAND flash
2 2
3 Required properties: 3 Required properties:
4 - compatible : "fsl,upm-nand". 4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select an 5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for 6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for 7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
8 8
9 Optional properties: 9 Optional properties:
>> 10 - fsl,upm-wait-flags : add chip-dependent short delays after running the
>> 11 UPM pattern (0x1), after writing a data byte (0x2) or after
>> 12 writing out a buffer (0x4).
10 - fsl,upm-addr-line-cs-offsets : address offse 13 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are us 14 The corresponding address lines are used to select the chip.
12 - gpios : may specify optional GPIOs connected 15 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GP 16 (R/B#). For multi-chip devices, "n" GPIO definitions are required
14 according to the number of chips. 17 according to the number of chips.
15 <<
16 Deprecated properties: <<
17 - fsl,upm-wait-flags : add chip-dependent shor <<
18 UPM pattern (0x1), after writing a dat <<
19 writing out a buffer (0x4). <<
20 - chip-delay : chip dependent delay for transf 18 - chip-delay : chip dependent delay for transferring data from array to
21 read registers (tR). Required if prope 19 read registers (tR). Required if property "gpios" is not used
22 (R/B# pins not connected). 20 (R/B# pins not connected).
23 21
24 Each flash chip described may optionally conta 22 Each flash chip described may optionally contain additional sub-nodes
25 describing partitions of the address space. Se !! 23 describing partitions of the address space. See partition.txt for more
26 detail. 24 detail.
27 25
28 Examples: 26 Examples:
29 27
30 upm@1,0 { 28 upm@1,0 {
31 compatible = "fsl,upm-nand"; 29 compatible = "fsl,upm-nand";
32 reg = <1 0 1>; 30 reg = <1 0 1>;
33 fsl,upm-addr-offset = <16>; 31 fsl,upm-addr-offset = <16>;
34 fsl,upm-cmd-offset = <8>; 32 fsl,upm-cmd-offset = <8>;
35 gpios = <&qe_pio_e 18 0>; 33 gpios = <&qe_pio_e 18 0>;
36 34
37 flash { 35 flash {
38 #address-cells = <1>; 36 #address-cells = <1>;
39 #size-cells = <1>; 37 #size-cells = <1>;
40 compatible = "..."; 38 compatible = "...";
41 39
42 partition@0 { 40 partition@0 {
43 ... 41 ...
44 }; 42 };
45 }; 43 };
46 }; 44 };
47 45
48 upm@3,0 { 46 upm@3,0 {
49 #address-cells = <0>; 47 #address-cells = <0>;
50 #size-cells = <0>; 48 #size-cells = <0>;
51 compatible = "tqc,tqm8548-upm-nand", " 49 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
52 reg = <3 0x0 0x800>; 50 reg = <3 0x0 0x800>;
53 fsl,upm-addr-offset = <0x10>; 51 fsl,upm-addr-offset = <0x10>;
54 fsl,upm-cmd-offset = <0x08>; 52 fsl,upm-cmd-offset = <0x08>;
55 /* Multi-chip NAND device */ 53 /* Multi-chip NAND device */
56 fsl,upm-addr-line-cs-offsets = <0x0 0x 54 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
>> 55 fsl,upm-wait-flags = <0x5>;
>> 56 chip-delay = <25>; // in micro-seconds
57 57
58 nand@0 { 58 nand@0 {
59 #address-cells = <1>; 59 #address-cells = <1>;
60 #size-cells = <1>; 60 #size-cells = <1>;
61 61
62 partition@0 { 62 partition@0 {
63 label = "fs"; 63 label = "fs";
64 reg = <0x00000000 64 reg = <0x00000000 0x10000000>;
65 }; 65 };
66 }; 66 };
67 }; 67 };
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