1 GPIO assisted NAND flash 1 GPIO assisted NAND flash
2 2
3 The GPIO assisted NAND flash uses a memory map 3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO 4 read/write the NAND commands and data and GPIO pins for the control
5 signals. 5 signals.
6 6
7 Required properties: 7 Required properties:
8 - compatible : "gpio-control-nand" 8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select an 9 - reg : should specify localbus chip select and size used for the chip. The
10 resource describes the data bus connected to 10 resource describes the data bus connected to the NAND flash and all accesses
11 are made in native endianness. 11 are made in native endianness.
12 - #address-cells, #size-cells : Must be presen 12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
13 representing partitions. 13 representing partitions.
14 - gpios : Specifies the GPIO pins to control t 14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
15 GPIO references is: RDY, nCE, ALE, CLE, and 15 GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
16 16
17 Optional properties: 17 Optional properties:
18 - bank-width : Width (in bytes) of the device. 18 - bank-width : Width (in bytes) of the device. If not present, the width
19 defaults to 1 byte. 19 defaults to 1 byte.
20 - chip-delay : chip dependent delay for transf 20 - chip-delay : chip dependent delay for transferring data from array to
21 read registers (tR). If not present then a 21 read registers (tR). If not present then a default of 20us is used.
22 - gpio-control-nand,io-sync-reg : A 64-bit phy 22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
23 location used to guard against bus reorderin 23 location used to guard against bus reordering with regards to accesses to
24 the GPIO's and the NAND flash data bus. If 24 the GPIO's and the NAND flash data bus. If present, then after changing
25 GPIO state and before and after command byte 25 GPIO state and before and after command byte writes, this register will be
26 read to ensure that the GPIO accesses have c 26 read to ensure that the GPIO accesses have completed.
27 27
28 The device tree may optionally contain sub-nod 28 The device tree may optionally contain sub-nodes describing partitions of the
29 address space. See mtd.yaml for more detail. 29 address space. See mtd.yaml for more detail.
30 30
31 Examples: 31 Examples:
32 32
33 gpio-nand@1,0 { 33 gpio-nand@1,0 {
34 compatible = "gpio-control-nand"; 34 compatible = "gpio-control-nand";
35 reg = <1 0x0000 0x2>; 35 reg = <1 0x0000 0x2>;
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <1>; 37 #size-cells = <1>;
38 gpios = <&banka 1 0>, /* RDY */ 38 gpios = <&banka 1 0>, /* RDY */
39 <0>, /* nCE */ 39 <0>, /* nCE */
40 <&banka 3 0>, /* ALE */ 40 <&banka 3 0>, /* ALE */
41 <&banka 4 0>, /* CLE */ 41 <&banka 4 0>, /* CLE */
42 <0>; /* nWP */ 42 <0>; /* nWP */
43 43
44 partition@0 { 44 partition@0 {
45 ... 45 ...
46 }; 46 };
47 }; 47 };
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