1 NXP LPC32xx SoC NAND MLC controller 1 NXP LPC32xx SoC NAND MLC controller
2 2
3 Required properties: 3 Required properties:
4 - compatible: "nxp,lpc3220-mlc" 4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller 5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification 6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write pro 7 - gpios: GPIO specification for NAND write protect
8 8
9 The following required properties are very con 9 The following required properties are very controller specific. See the LPC32xx
10 User Manual 7.5.14 MLC NAND Timing Register (t 10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
11 Hz, to make them independent of actual clock s 11 Hz, to make them independent of actual clock speed and to provide for good
12 accuracy:) 12 accuracy:)
13 - nxp,tcea_delay: TCEA_DELAY 13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY 14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA 15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH 16 - nxp,rd_high: RD_HIGH
17 - nxp,rd_low: RD_LOW 17 - nxp,rd_low: RD_LOW
18 - nxp,wr_high: WR_HIGH 18 - nxp,wr_high: WR_HIGH
19 - nxp,wr_low: WR_LOW 19 - nxp,wr_low: WR_LOW
20 20
21 Optional subnodes: 21 Optional subnodes:
22 - Partitions, see Documentation/devicetree/bin 22 - Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
23 23
24 Example: 24 Example:
25 25
26 mlc: flash@200a8000 { 26 mlc: flash@200a8000 {
27 compatible = "nxp,lpc3220-mlc" 27 compatible = "nxp,lpc3220-mlc";
28 reg = <0x200A8000 0x11000>; 28 reg = <0x200A8000 0x11000>;
29 interrupts = <11 0>; 29 interrupts = <11 0>;
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <1>; 31 #size-cells = <1>;
32 32
33 nxp,tcea-delay = <333333333>; 33 nxp,tcea-delay = <333333333>;
34 nxp,busy-delay = <10000000>; 34 nxp,busy-delay = <10000000>;
35 nxp,nand-ta = <18181818>; 35 nxp,nand-ta = <18181818>;
36 nxp,rd-high = <31250000>; 36 nxp,rd-high = <31250000>;
37 nxp,rd-low = <45454545>; 37 nxp,rd-low = <45454545>;
38 nxp,wr-high = <40000000>; 38 nxp,wr-high = <40000000>;
39 nxp,wr-low = <83333333>; 39 nxp,wr-low = <83333333>;
40 gpios = <&gpio 5 19 1>; /* GPO 40 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
41 41
42 mtd0@00000000 { 42 mtd0@00000000 {
43 label = "boot"; 43 label = "boot";
44 reg = <0x00000000 0x00 44 reg = <0x00000000 0x00064000>;
45 read-only; 45 read-only;
46 }; 46 };
47 47
48 ... 48 ...
49 49
50 }; 50 };
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