1 NXP LPC32xx SoC NAND SLC controller 1 NXP LPC32xx SoC NAND SLC controller
2 2
3 Required properties: 3 Required properties:
4 - compatible: "nxp,lpc3220-slc" 4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller 5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on fl 6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write pro 7 - gpios: GPIO specification for NAND write protect
8 8
9 The following required properties are very con 9 The following required properties are very controller specific. See the LPC32xx
10 User Manual: 10 User Manual:
11 - nxp,wdr-clks: Delay before Ready signal is t 11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is t 12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
13 (The following values are specified in Hz, to 13 (The following values are specified in Hz, to make them independent of actual
14 clock speed:) 14 clock speed:)
15 - nxp,wwidth: Write pulse width (W_WIDTH) 15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD) 16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP) 17 - nxp,wsetup: Write setup time (W_SETUP)
18 - nxp,rwidth: Read pulse width (R_WIDTH) 18 - nxp,rwidth: Read pulse width (R_WIDTH)
19 - nxp,rhold: Read hold time (R_HOLD) 19 - nxp,rhold: Read hold time (R_HOLD)
20 - nxp,rsetup: Read setup time (R_SETUP) 20 - nxp,rsetup: Read setup time (R_SETUP)
21 21
22 Optional subnodes: 22 Optional subnodes:
23 - Partitions, see Documentation/devicetree/bin 23 - Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml
24 24
25 Example: 25 Example:
26 26
27 slc: flash@20020000 { 27 slc: flash@20020000 {
28 compatible = "nxp,lpc3220-slc" 28 compatible = "nxp,lpc3220-slc";
29 reg = <0x20020000 0x1000>; 29 reg = <0x20020000 0x1000>;
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <1>; 31 #size-cells = <1>;
32 32
33 nxp,wdr-clks = <14>; 33 nxp,wdr-clks = <14>;
34 nxp,wwidth = <40000000>; 34 nxp,wwidth = <40000000>;
35 nxp,whold = <100000000>; 35 nxp,whold = <100000000>;
36 nxp,wsetup = <100000000>; 36 nxp,wsetup = <100000000>;
37 nxp,rdr-clks = <14>; 37 nxp,rdr-clks = <14>;
38 nxp,rwidth = <40000000>; 38 nxp,rwidth = <40000000>;
39 nxp,rhold = <66666666>; 39 nxp,rhold = <66666666>;
40 nxp,rsetup = <100000000>; 40 nxp,rsetup = <100000000>;
41 nand-on-flash-bbt; 41 nand-on-flash-bbt;
42 gpios = <&gpio 5 19 1>; /* GPO 42 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
43 43
44 mtd0@00000000 { 44 mtd0@00000000 {
45 label = "phy3250-boot" 45 label = "phy3250-boot";
46 reg = <0x00000000 0x00 46 reg = <0x00000000 0x00064000>;
47 read-only; 47 read-only;
48 }; 48 };
49 49
50 ... 50 ...
51 51
52 }; 52 };
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