1 # SPDX-License-Identifier: (GPL-2.0-only OR BS !! 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-co 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NAND Controller Common Properties !! 7 title: NAND Chip and NAND Controller Generic Binding
8 8
9 maintainers: 9 maintainers:
10 - Miquel Raynal <miquel.raynal@bootlin.com> 10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at> 11 - Richard Weinberger <richard@nod.at>
12 12
13 description: | 13 description: |
14 The NAND controller should be represented wi 14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller s 15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This 16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers support 17 enforced even for simple controllers supporting only one chip.
18 18
>> 19 The ECC strength and ECC step size properties define the user
>> 20 desires in terms of correction capability of a controller. Together,
>> 21 they request the ECC engine to correct {strength} bit errors per
>> 22 {size} bytes.
>> 23
>> 24 The interpretation of these parameters is implementation-defined, so
>> 25 not all implementations must support all possible
>> 26 combinations. However, implementations are encouraged to further
>> 27 specify the value(s) they support.
>> 28
19 properties: 29 properties:
20 $nodename: 30 $nodename:
21 pattern: "^nand-controller(@.*)?" 31 pattern: "^nand-controller(@.*)?"
22 32
23 "#address-cells": 33 "#address-cells":
24 const: 1 34 const: 1
25 35
26 "#size-cells": 36 "#size-cells":
27 const: 0 37 const: 0
28 38
29 ranges: true 39 ranges: true
30 40
31 cs-gpios: <<
32 description: <<
33 Array of chip-select available to the co <<
34 entries are a 1:1 mapping of the availab <<
35 NAND controller (even if they are not us <<
36 chip-select as needed may follow and sho <<
37 lines. 'reg' entries of the NAND chip su <<
38 this array when this property is present <<
39 minItems: 1 <<
40 maxItems: 8 <<
41 <<
42 patternProperties: 41 patternProperties:
43 "^nand@[a-f0-9]$": 42 "^nand@[a-f0-9]$":
44 type: object 43 type: object
45 $ref: raw-nand-chip.yaml# !! 44 properties:
>> 45 reg:
>> 46 description:
>> 47 Contains the chip-select IDs.
>> 48
>> 49 nand-ecc-mode:
>> 50 description:
>> 51 Desired ECC engine, either hardware (most of the time
>> 52 embedded in the NAND controller) or software correction
>> 53 (Linux will handle the calculations). soft_bch is deprecated
>> 54 and should be replaced by soft and nand-ecc-algo.
>> 55 $ref: /schemas/types.yaml#/definitions/string
>> 56 enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
>> 57
>> 58 nand-ecc-engine:
>> 59 allOf:
>> 60 - $ref: /schemas/types.yaml#/definitions/phandle
>> 61 description: |
>> 62 A phandle on the hardware ECC engine if any. There are
>> 63 basically three possibilities:
>> 64 1/ The ECC engine is part of the NAND controller, in this
>> 65 case the phandle should reference the parent node.
>> 66 2/ The ECC engine is part of the NAND part (on-die), in this
>> 67 case the phandle should reference the node itself.
>> 68 3/ The ECC engine is external, in this case the phandle should
>> 69 reference the specific ECC engine node.
>> 70
>> 71 nand-use-soft-ecc-engine:
>> 72 type: boolean
>> 73 description: Use a software ECC engine.
>> 74
>> 75 nand-no-ecc-engine:
>> 76 type: boolean
>> 77 description: Do not use any ECC correction.
>> 78
>> 79 nand-ecc-placement:
>> 80 allOf:
>> 81 - $ref: /schemas/types.yaml#/definitions/string
>> 82 - enum: [ oob, interleaved ]
>> 83 description:
>> 84 Location of the ECC bytes. This location is unknown by default
>> 85 but can be explicitly set to "oob", if all ECC bytes are
>> 86 known to be stored in the OOB area, or "interleaved" if ECC
>> 87 bytes will be interleaved with regular data in the main area.
>> 88
>> 89 nand-ecc-algo:
>> 90 description:
>> 91 Desired ECC algorithm.
>> 92 $ref: /schemas/types.yaml#/definitions/string
>> 93 enum: [hamming, bch, rs]
>> 94
>> 95 nand-bus-width:
>> 96 description:
>> 97 Bus width to the NAND chip
>> 98 $ref: /schemas/types.yaml#/definitions/uint32
>> 99 enum: [8, 16]
>> 100 default: 8
>> 101
>> 102 nand-on-flash-bbt:
>> 103 $ref: /schemas/types.yaml#/definitions/flag
>> 104 description:
>> 105 With this property, the OS will search the device for a Bad
>> 106 Block Table (BBT). If not found, it will create one, reserve
>> 107 a few blocks at the end of the device to store it and update
>> 108 it as the device ages. Otherwise, the out-of-band area of a
>> 109 few pages of all the blocks will be scanned at boot time to
>> 110 find Bad Block Markers (BBM). These markers will help to
>> 111 build a volatile BBT in RAM.
>> 112
>> 113 nand-ecc-strength:
>> 114 description:
>> 115 Maximum number of bits that can be corrected per ECC step.
>> 116 $ref: /schemas/types.yaml#/definitions/uint32
>> 117 minimum: 1
>> 118
>> 119 nand-ecc-step-size:
>> 120 description:
>> 121 Number of data bytes covered by a single ECC step.
>> 122 $ref: /schemas/types.yaml#/definitions/uint32
>> 123 minimum: 1
>> 124
>> 125 nand-ecc-maximize:
>> 126 $ref: /schemas/types.yaml#/definitions/flag
>> 127 description:
>> 128 Whether or not the ECC strength should be maximized. The
>> 129 maximum ECC strength is both controller and chip
>> 130 dependent. The ECC engine has to select the ECC config
>> 131 providing the best strength and taking the OOB area size
>> 132 constraint into account. This is particularly useful when
>> 133 only the in-band area is used by the upper layers, and you
>> 134 want to make your NAND as reliable as possible.
>> 135
>> 136 nand-is-boot-medium:
>> 137 $ref: /schemas/types.yaml#/definitions/flag
>> 138 description:
>> 139 Whether or not the NAND chip is a boot medium. Drivers might
>> 140 use this information to select ECC algorithms supported by
>> 141 the boot ROM or similar restrictions.
>> 142
>> 143 nand-rb:
>> 144 $ref: /schemas/types.yaml#/definitions/uint32-array
>> 145 description:
>> 146 Contains the native Ready/Busy IDs.
>> 147
>> 148 rb-gpios:
>> 149 description:
>> 150 Contains one or more GPIO descriptor (the numper of descriptor
>> 151 depends on the number of R/B pins exposed by the flash) for the
>> 152 Ready/Busy pins. Active state refers to the NAND ready state and
>> 153 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
>> 154
>> 155 required:
>> 156 - reg
46 157
47 required: 158 required:
48 - "#address-cells" 159 - "#address-cells"
49 - "#size-cells" 160 - "#size-cells"
50 161
51 # This is a generic file other binding inherit <<
52 additionalProperties: true 162 additionalProperties: true
53 163
54 examples: 164 examples:
55 - | 165 - |
56 nand-controller { 166 nand-controller {
57 #address-cells = <1>; 167 #address-cells = <1>;
58 #size-cells = <0>; 168 #size-cells = <0>;
59 cs-gpios = <0>, <&gpioA 1>; /* A single <<
60 169
61 /* controller specific properties */ 170 /* controller specific properties */
62 171
63 nand@0 { 172 nand@0 {
64 reg = <0>; /* Native CS */ !! 173 reg = <0>;
65 /* NAND chip specific properties */ !! 174 nand-ecc-mode = "soft";
66 }; !! 175 nand-ecc-algo = "bch";
67 176
68 nand@1 { !! 177 /* NAND chip specific properties */
69 reg = <1>; /* GPIO CS */ <<
70 }; 178 };
71 }; 179 };
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