1 # SPDX-License-Identifier: (GPL-2.0-only OR BS !! 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-co 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NAND Controller Common Properties !! 7 title: NAND Chip and NAND Controller Generic Binding
8 8
9 maintainers: 9 maintainers:
10 - Miquel Raynal <miquel.raynal@bootlin.com> 10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at> 11 - Richard Weinberger <richard@nod.at>
12 12
13 description: | 13 description: |
14 The NAND controller should be represented wi 14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller s 15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This 16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers support 17 enforced even for simple controllers supporting only one chip.
18 18
>> 19 The ECC strength and ECC step size properties define the user
>> 20 desires in terms of correction capability of a controller. Together,
>> 21 they request the ECC engine to correct {strength} bit errors per
>> 22 {size} bytes.
>> 23
>> 24 The interpretation of these parameters is implementation-defined, so
>> 25 not all implementations must support all possible
>> 26 combinations. However, implementations are encouraged to further
>> 27 specify the value(s) they support.
>> 28
19 properties: 29 properties:
20 $nodename: 30 $nodename:
21 pattern: "^nand-controller(@.*)?" 31 pattern: "^nand-controller(@.*)?"
22 32
23 "#address-cells": 33 "#address-cells":
24 const: 1 34 const: 1
25 35
26 "#size-cells": 36 "#size-cells":
27 const: 0 37 const: 0
28 38
29 ranges: true 39 ranges: true
30 40
31 cs-gpios: <<
32 description: <<
33 Array of chip-select available to the co <<
34 entries are a 1:1 mapping of the availab <<
35 NAND controller (even if they are not us <<
36 chip-select as needed may follow and sho <<
37 lines. 'reg' entries of the NAND chip su <<
38 this array when this property is present <<
39 minItems: 1 <<
40 maxItems: 8 <<
41 <<
42 patternProperties: 41 patternProperties:
43 "^nand@[a-f0-9]$": 42 "^nand@[a-f0-9]$":
44 type: object 43 type: object
45 $ref: raw-nand-chip.yaml# !! 44 properties:
>> 45 reg:
>> 46 description:
>> 47 Contains the native Ready/Busy IDs.
>> 48
>> 49 nand-ecc-engine:
>> 50 allOf:
>> 51 - $ref: /schemas/types.yaml#/definitions/phandle
>> 52 description: |
>> 53 A phandle on the hardware ECC engine if any. There are
>> 54 basically three possibilities:
>> 55 1/ The ECC engine is part of the NAND controller, in this
>> 56 case the phandle should reference the parent node.
>> 57 2/ The ECC engine is part of the NAND part (on-die), in this
>> 58 case the phandle should reference the node itself.
>> 59 3/ The ECC engine is external, in this case the phandle should
>> 60 reference the specific ECC engine node.
>> 61
>> 62 nand-use-soft-ecc-engine:
>> 63 type: boolean
>> 64 description: Use a software ECC engine.
>> 65
>> 66 nand-no-ecc-engine:
>> 67 type: boolean
>> 68 description: Do not use any ECC correction.
>> 69
>> 70 nand-ecc-placement:
>> 71 allOf:
>> 72 - $ref: /schemas/types.yaml#/definitions/string
>> 73 - enum: [ oob, interleaved ]
>> 74 description:
>> 75 Location of the ECC bytes. This location is unknown by default
>> 76 but can be explicitly set to "oob", if all ECC bytes are
>> 77 known to be stored in the OOB area, or "interleaved" if ECC
>> 78 bytes will be interleaved with regular data in the main area.
>> 79
>> 80 nand-ecc-algo:
>> 81 description:
>> 82 Desired ECC algorithm.
>> 83 $ref: /schemas/types.yaml#/definitions/string
>> 84 enum: [hamming, bch, rs]
>> 85
>> 86 nand-bus-width:
>> 87 description:
>> 88 Bus width to the NAND chip
>> 89 $ref: /schemas/types.yaml#/definitions/uint32
>> 90 enum: [8, 16]
>> 91 default: 8
>> 92
>> 93 nand-on-flash-bbt:
>> 94 $ref: /schemas/types.yaml#/definitions/flag
>> 95 description:
>> 96 With this property, the OS will search the device for a Bad
>> 97 Block Table (BBT). If not found, it will create one, reserve
>> 98 a few blocks at the end of the device to store it and update
>> 99 it as the device ages. Otherwise, the out-of-band area of a
>> 100 few pages of all the blocks will be scanned at boot time to
>> 101 find Bad Block Markers (BBM). These markers will help to
>> 102 build a volatile BBT in RAM.
>> 103
>> 104 nand-ecc-strength:
>> 105 description:
>> 106 Maximum number of bits that can be corrected per ECC step.
>> 107 $ref: /schemas/types.yaml#/definitions/uint32
>> 108 minimum: 1
>> 109
>> 110 nand-ecc-step-size:
>> 111 description:
>> 112 Number of data bytes covered by a single ECC step.
>> 113 $ref: /schemas/types.yaml#/definitions/uint32
>> 114 minimum: 1
>> 115
>> 116 nand-ecc-maximize:
>> 117 $ref: /schemas/types.yaml#/definitions/flag
>> 118 description:
>> 119 Whether or not the ECC strength should be maximized. The
>> 120 maximum ECC strength is both controller and chip
>> 121 dependent. The ECC engine has to select the ECC config
>> 122 providing the best strength and taking the OOB area size
>> 123 constraint into account. This is particularly useful when
>> 124 only the in-band area is used by the upper layers, and you
>> 125 want to make your NAND as reliable as possible.
>> 126
>> 127 nand-is-boot-medium:
>> 128 $ref: /schemas/types.yaml#/definitions/flag
>> 129 description:
>> 130 Whether or not the NAND chip is a boot medium. Drivers might
>> 131 use this information to select ECC algorithms supported by
>> 132 the boot ROM or similar restrictions.
>> 133
>> 134 nand-rb:
>> 135 $ref: /schemas/types.yaml#/definitions/uint32-array
>> 136 description:
>> 137 Contains the native Ready/Busy IDs.
>> 138
>> 139 rb-gpios:
>> 140 description:
>> 141 Contains one or more GPIO descriptor (the numper of descriptor
>> 142 depends on the number of R/B pins exposed by the flash) for the
>> 143 Ready/Busy pins. Active state refers to the NAND ready state and
>> 144 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
>> 145
>> 146 required:
>> 147 - reg
46 148
47 required: 149 required:
48 - "#address-cells" 150 - "#address-cells"
49 - "#size-cells" 151 - "#size-cells"
50 152
51 # This is a generic file other binding inherit <<
52 additionalProperties: true 153 additionalProperties: true
53 154
54 examples: 155 examples:
55 - | 156 - |
56 nand-controller { 157 nand-controller {
57 #address-cells = <1>; 158 #address-cells = <1>;
58 #size-cells = <0>; 159 #size-cells = <0>;
59 cs-gpios = <0>, <&gpioA 1>; /* A single <<
60 160
61 /* controller specific properties */ 161 /* controller specific properties */
62 162
63 nand@0 { 163 nand@0 {
64 reg = <0>; /* Native CS */ !! 164 reg = <0>;
65 /* NAND chip specific properties */ !! 165 nand-use-soft-ecc-engine;
66 }; !! 166 nand-ecc-algo = "bch";
67 167
68 nand@1 { !! 168 /* controller specific properties */
69 reg = <1>; /* GPIO CS */ <<
70 }; 169 };
71 }; 170 };
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