1 # SPDX-License-Identifier: (GPL-2.0-only OR BS !! 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-co 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NAND Controller Common Properties !! 7 title: NAND Chip and NAND Controller Generic Binding
8 8
9 maintainers: 9 maintainers:
10 - Miquel Raynal <miquel.raynal@bootlin.com> 10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at> 11 - Richard Weinberger <richard@nod.at>
12 12
13 description: | 13 description: |
14 The NAND controller should be represented wi 14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller s 15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This 16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers support 17 enforced even for simple controllers supporting only one chip.
18 18
>> 19 The ECC strength and ECC step size properties define the user
>> 20 desires in terms of correction capability of a controller. Together,
>> 21 they request the ECC engine to correct {strength} bit errors per
>> 22 {size} bytes.
>> 23
>> 24 The interpretation of these parameters is implementation-defined, so
>> 25 not all implementations must support all possible
>> 26 combinations. However, implementations are encouraged to further
>> 27 specify the value(s) they support.
>> 28
19 properties: 29 properties:
20 $nodename: 30 $nodename:
21 pattern: "^nand-controller(@.*)?" 31 pattern: "^nand-controller(@.*)?"
22 32
23 "#address-cells": 33 "#address-cells":
24 const: 1 34 const: 1
25 35
26 "#size-cells": 36 "#size-cells":
27 const: 0 37 const: 0
28 38
29 ranges: true 39 ranges: true
30 40
31 cs-gpios: <<
32 description: <<
33 Array of chip-select available to the co <<
34 entries are a 1:1 mapping of the availab <<
35 NAND controller (even if they are not us <<
36 chip-select as needed may follow and sho <<
37 lines. 'reg' entries of the NAND chip su <<
38 this array when this property is present <<
39 minItems: 1 <<
40 maxItems: 8 <<
41 <<
42 patternProperties: 41 patternProperties:
43 "^nand@[a-f0-9]$": 42 "^nand@[a-f0-9]$":
44 type: object !! 43 properties:
45 $ref: raw-nand-chip.yaml# !! 44 reg:
>> 45 description:
>> 46 Contains the native Ready/Busy IDs.
>> 47
>> 48 nand-ecc-mode:
>> 49 allOf:
>> 50 - $ref: /schemas/types.yaml#/definitions/string
>> 51 - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
>> 52 description:
>> 53 Desired ECC engine, either hardware (most of the time
>> 54 embedded in the NAND controller) or software correction
>> 55 (Linux will handle the calculations). soft_bch is deprecated
>> 56 and should be replaced by soft and nand-ecc-algo.
>> 57
>> 58 nand-ecc-algo:
>> 59 allOf:
>> 60 - $ref: /schemas/types.yaml#/definitions/string
>> 61 - enum: [ hamming, bch, rs ]
>> 62 description:
>> 63 Desired ECC algorithm.
>> 64
>> 65 nand-bus-width:
>> 66 allOf:
>> 67 - $ref: /schemas/types.yaml#/definitions/uint32
>> 68 - enum: [ 8, 16 ]
>> 69 - default: 8
>> 70 description:
>> 71 Bus width to the NAND chip
>> 72
>> 73 nand-on-flash-bbt:
>> 74 $ref: /schemas/types.yaml#/definitions/flag
>> 75 description:
>> 76 With this property, the OS will search the device for a Bad
>> 77 Block Table (BBT). If not found, it will create one, reserve
>> 78 a few blocks at the end of the device to store it and update
>> 79 it as the device ages. Otherwise, the out-of-band area of a
>> 80 few pages of all the blocks will be scanned at boot time to
>> 81 find Bad Block Markers (BBM). These markers will help to
>> 82 build a volatile BBT in RAM.
>> 83
>> 84 nand-ecc-strength:
>> 85 allOf:
>> 86 - $ref: /schemas/types.yaml#/definitions/uint32
>> 87 - minimum: 1
>> 88 description:
>> 89 Maximum number of bits that can be corrected per ECC step.
>> 90
>> 91 nand-ecc-step-size:
>> 92 allOf:
>> 93 - $ref: /schemas/types.yaml#/definitions/uint32
>> 94 - minimum: 1
>> 95 description:
>> 96 Number of data bytes covered by a single ECC step.
>> 97
>> 98 nand-ecc-maximize:
>> 99 $ref: /schemas/types.yaml#/definitions/flag
>> 100 description:
>> 101 Whether or not the ECC strength should be maximized. The
>> 102 maximum ECC strength is both controller and chip
>> 103 dependent. The ECC engine has to select the ECC config
>> 104 providing the best strength and taking the OOB area size
>> 105 constraint into account. This is particularly useful when
>> 106 only the in-band area is used by the upper layers, and you
>> 107 want to make your NAND as reliable as possible.
>> 108
>> 109 nand-is-boot-medium:
>> 110 $ref: /schemas/types.yaml#/definitions/flag
>> 111 description:
>> 112 Whether or not the NAND chip is a boot medium. Drivers might
>> 113 use this information to select ECC algorithms supported by
>> 114 the boot ROM or similar restrictions.
>> 115
>> 116 nand-rb:
>> 117 $ref: /schemas/types.yaml#/definitions/uint32-array
>> 118 description:
>> 119 Contains the native Ready/Busy IDs.
>> 120
>> 121 required:
>> 122 - reg
46 123
47 required: 124 required:
48 - "#address-cells" 125 - "#address-cells"
49 - "#size-cells" 126 - "#size-cells"
50 127
51 # This is a generic file other binding inherit <<
52 additionalProperties: true <<
53 <<
54 examples: 128 examples:
55 - | 129 - |
56 nand-controller { 130 nand-controller {
57 #address-cells = <1>; 131 #address-cells = <1>;
58 #size-cells = <0>; 132 #size-cells = <0>;
59 cs-gpios = <0>, <&gpioA 1>; /* A single <<
60 133
61 /* controller specific properties */ 134 /* controller specific properties */
62 135
63 nand@0 { 136 nand@0 {
64 reg = <0>; /* Native CS */ !! 137 reg = <0>;
65 /* NAND chip specific properties */ !! 138 nand-ecc-mode = "soft";
66 }; !! 139 nand-ecc-algo = "bch";
67 140
68 nand@1 { !! 141 /* controller specific properties */
69 reg = <1>; /* GPIO CS */ <<
70 }; 142 };
71 }; 143 };
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