1 # SPDX-License-Identifier: (GPL-2.0-only OR BS !! 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-co 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NAND Controller Common Properties 7 title: NAND Controller Common Properties
8 8
9 maintainers: 9 maintainers:
10 - Miquel Raynal <miquel.raynal@bootlin.com> 10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at> 11 - Richard Weinberger <richard@nod.at>
12 12
13 description: | 13 description: |
14 The NAND controller should be represented wi 14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller s 15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This 16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers support 17 enforced even for simple controllers supporting only one chip.
18 18
>> 19 The ECC strength and ECC step size properties define the user
>> 20 desires in terms of correction capability of a controller. Together,
>> 21 they request the ECC engine to correct {strength} bit errors per
>> 22 {size} bytes.
>> 23
>> 24 The interpretation of these parameters is implementation-defined, so
>> 25 not all implementations must support all possible
>> 26 combinations. However, implementations are encouraged to further
>> 27 specify the value(s) they support.
>> 28
19 properties: 29 properties:
20 $nodename: 30 $nodename:
21 pattern: "^nand-controller(@.*)?" 31 pattern: "^nand-controller(@.*)?"
22 32
23 "#address-cells": 33 "#address-cells":
24 const: 1 34 const: 1
25 35
26 "#size-cells": 36 "#size-cells":
27 const: 0 37 const: 0
28 38
29 ranges: true 39 ranges: true
30 40
31 cs-gpios: 41 cs-gpios:
32 description: 42 description:
33 Array of chip-select available to the co 43 Array of chip-select available to the controller. The first
34 entries are a 1:1 mapping of the availab 44 entries are a 1:1 mapping of the available chip-select on the
35 NAND controller (even if they are not us 45 NAND controller (even if they are not used). As many additional
36 chip-select as needed may follow and sho 46 chip-select as needed may follow and should be phandles of GPIO
37 lines. 'reg' entries of the NAND chip su 47 lines. 'reg' entries of the NAND chip subnodes become indexes of
38 this array when this property is present 48 this array when this property is present.
39 minItems: 1 49 minItems: 1
40 maxItems: 8 50 maxItems: 8
41 51
42 patternProperties: 52 patternProperties:
43 "^nand@[a-f0-9]$": 53 "^nand@[a-f0-9]$":
44 type: object !! 54 $ref: "nand-chip.yaml#"
45 $ref: raw-nand-chip.yaml# !! 55
>> 56 properties:
>> 57 reg:
>> 58 description:
>> 59 Contains the chip-select IDs.
>> 60
>> 61 nand-ecc-placement:
>> 62 description:
>> 63 Location of the ECC bytes. This location is unknown by default
>> 64 but can be explicitly set to "oob", if all ECC bytes are
>> 65 known to be stored in the OOB area, or "interleaved" if ECC
>> 66 bytes will be interleaved with regular data in the main area.
>> 67 $ref: /schemas/types.yaml#/definitions/string
>> 68 enum: [ oob, interleaved ]
>> 69
>> 70 nand-bus-width:
>> 71 description:
>> 72 Bus width to the NAND chip
>> 73 $ref: /schemas/types.yaml#/definitions/uint32
>> 74 enum: [8, 16]
>> 75 default: 8
>> 76
>> 77 nand-on-flash-bbt:
>> 78 description:
>> 79 With this property, the OS will search the device for a Bad
>> 80 Block Table (BBT). If not found, it will create one, reserve
>> 81 a few blocks at the end of the device to store it and update
>> 82 it as the device ages. Otherwise, the out-of-band area of a
>> 83 few pages of all the blocks will be scanned at boot time to
>> 84 find Bad Block Markers (BBM). These markers will help to
>> 85 build a volatile BBT in RAM.
>> 86 $ref: /schemas/types.yaml#/definitions/flag
>> 87
>> 88 nand-ecc-maximize:
>> 89 description:
>> 90 Whether or not the ECC strength should be maximized. The
>> 91 maximum ECC strength is both controller and chip
>> 92 dependent. The ECC engine has to select the ECC config
>> 93 providing the best strength and taking the OOB area size
>> 94 constraint into account. This is particularly useful when
>> 95 only the in-band area is used by the upper layers, and you
>> 96 want to make your NAND as reliable as possible.
>> 97 $ref: /schemas/types.yaml#/definitions/flag
>> 98
>> 99 nand-is-boot-medium:
>> 100 description:
>> 101 Whether or not the NAND chip is a boot medium. Drivers might
>> 102 use this information to select ECC algorithms supported by
>> 103 the boot ROM or similar restrictions.
>> 104 $ref: /schemas/types.yaml#/definitions/flag
>> 105
>> 106 nand-rb:
>> 107 description:
>> 108 Contains the native Ready/Busy IDs.
>> 109 $ref: /schemas/types.yaml#/definitions/uint32-array
>> 110
>> 111 rb-gpios:
>> 112 description:
>> 113 Contains one or more GPIO descriptor (the numper of descriptor
>> 114 depends on the number of R/B pins exposed by the flash) for the
>> 115 Ready/Busy pins. Active state refers to the NAND ready state and
>> 116 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
>> 117
>> 118 wp-gpios:
>> 119 description:
>> 120 Contains one GPIO descriptor for the Write Protect pin.
>> 121 Active state refers to the NAND Write Protect state and should be
>> 122 set to GPIOD_ACTIVE_LOW unless the signal is inverted.
>> 123 maxItems: 1
>> 124
>> 125 required:
>> 126 - reg
46 127
47 required: 128 required:
48 - "#address-cells" 129 - "#address-cells"
49 - "#size-cells" 130 - "#size-cells"
50 131
51 # This is a generic file other binding inherit 132 # This is a generic file other binding inherit from and extend
52 additionalProperties: true 133 additionalProperties: true
53 134
54 examples: 135 examples:
55 - | 136 - |
56 nand-controller { 137 nand-controller {
57 #address-cells = <1>; 138 #address-cells = <1>;
58 #size-cells = <0>; 139 #size-cells = <0>;
59 cs-gpios = <0>, <&gpioA 1>; /* A single 140 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
60 141
61 /* controller specific properties */ 142 /* controller specific properties */
62 143
63 nand@0 { 144 nand@0 {
64 reg = <0>; /* Native CS */ 145 reg = <0>; /* Native CS */
65 /* NAND chip specific properties */ 146 /* NAND chip specific properties */
66 }; 147 };
67 148
68 nand@1 { 149 nand@1 {
69 reg = <1>; /* GPIO CS */ 150 reg = <1>; /* GPIO CS */
70 }; 151 };
71 }; 152 };
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