1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-co 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NAND Controller Common Properties 7 title: NAND Controller Common Properties
8 8
9 maintainers: 9 maintainers:
10 - Miquel Raynal <miquel.raynal@bootlin.com> 10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at> 11 - Richard Weinberger <richard@nod.at>
12 12
13 description: | 13 description: |
14 The NAND controller should be represented wi 14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller s 15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This 16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers support 17 enforced even for simple controllers supporting only one chip.
18 18
19 properties: 19 properties:
20 $nodename: 20 $nodename:
21 pattern: "^nand-controller(@.*)?" 21 pattern: "^nand-controller(@.*)?"
22 22
23 "#address-cells": 23 "#address-cells":
24 const: 1 24 const: 1
25 25
26 "#size-cells": 26 "#size-cells":
27 const: 0 27 const: 0
28 28
29 ranges: true 29 ranges: true
30 30
31 cs-gpios: 31 cs-gpios:
32 description: 32 description:
33 Array of chip-select available to the co 33 Array of chip-select available to the controller. The first
34 entries are a 1:1 mapping of the availab 34 entries are a 1:1 mapping of the available chip-select on the
35 NAND controller (even if they are not us 35 NAND controller (even if they are not used). As many additional
36 chip-select as needed may follow and sho 36 chip-select as needed may follow and should be phandles of GPIO
37 lines. 'reg' entries of the NAND chip su 37 lines. 'reg' entries of the NAND chip subnodes become indexes of
38 this array when this property is present 38 this array when this property is present.
39 minItems: 1 39 minItems: 1
40 maxItems: 8 40 maxItems: 8
41 41
42 patternProperties: 42 patternProperties:
43 "^nand@[a-f0-9]$": 43 "^nand@[a-f0-9]$":
44 type: object 44 type: object
45 $ref: raw-nand-chip.yaml# 45 $ref: raw-nand-chip.yaml#
46 46
47 required: 47 required:
48 - "#address-cells" 48 - "#address-cells"
49 - "#size-cells" 49 - "#size-cells"
50 50
51 # This is a generic file other binding inherit 51 # This is a generic file other binding inherit from and extend
52 additionalProperties: true 52 additionalProperties: true
53 53
54 examples: 54 examples:
55 - | 55 - |
56 nand-controller { 56 nand-controller {
57 #address-cells = <1>; 57 #address-cells = <1>;
58 #size-cells = <0>; 58 #size-cells = <0>;
59 cs-gpios = <0>, <&gpioA 1>; /* A single 59 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
60 60
61 /* controller specific properties */ 61 /* controller specific properties */
62 62
63 nand@0 { 63 nand@0 {
64 reg = <0>; /* Native CS */ 64 reg = <0>; /* Native CS */
65 /* NAND chip specific properties */ 65 /* NAND chip specific properties */
66 }; 66 };
67 67
68 nand@1 { 68 nand@1 {
69 reg = <1>; /* GPIO CS */ 69 reg = <1>; /* GPIO CS */
70 }; 70 };
71 }; 71 };
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