1 NVIDIA Tegra NAND Flash controller 1 NVIDIA Tegra NAND Flash controller
2 2
3 Required properties: 3 Required properties:
4 - compatible: Must be one of: 4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand" 5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range 6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC cont 7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry 8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details 9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entr 10 - clock-names: Must include the following entries:
11 - nand 11 - nand
12 - resets: Must contain an entry for each entry 12 - resets: Must contain an entry for each entry in reset-names.
13 See ../reset/reset.txt for details. 13 See ../reset/reset.txt for details.
14 - reset-names: Must include the following entr 14 - reset-names: Must include the following entries:
15 - nand 15 - nand
16 16
17 Optional children nodes: 17 Optional children nodes:
18 Individual NAND chips are children of the NAND 18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported. 19 only one NAND chip supported.
20 20
21 Required children node properties: 21 Required children node properties:
22 - reg: An integer ranging from 1 to 6 represen 22 - reg: An integer ranging from 1 to 6 representing the CS line to use.
23 23
24 Optional children node properties: 24 Optional children node properties:
25 - nand-ecc-mode: String, operation mode of the 25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
26 "hw" is supported. 26 "hw" is supported.
27 - nand-ecc-algo: string, algorithm of NAND ECC 27 - nand-ecc-algo: string, algorithm of NAND ECC.
28 Supported values with "hw" EC 28 Supported values with "hw" ECC mode are: "rs", "bch".
29 - nand-bus-width : See nand-controller.yaml 29 - nand-bus-width : See nand-controller.yaml
30 - nand-on-flash-bbt: See nand-controller.yaml 30 - nand-on-flash-bbt: See nand-controller.yaml
31 - nand-ecc-strength: integer representing the 31 - nand-ecc-strength: integer representing the number of bits to correct
32 per ECC step (always 512) 32 per ECC step (always 512). Supported strength using HW ECC
33 modes are: 33 modes are:
34 - RS: 4, 6, 8 34 - RS: 4, 6, 8
35 - BCH: 4, 8, 14, 16 35 - BCH: 4, 8, 14, 16
36 - nand-ecc-maximize: See nand-controller.yaml 36 - nand-ecc-maximize: See nand-controller.yaml
37 - nand-is-boot-medium: Makes sure only ECC str 37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
38 are chosen. 38 are chosen.
39 - wp-gpios: GPIO specifier for the write prote 39 - wp-gpios: GPIO specifier for the write protect pin.
40 40
41 Optional child node of NAND chip nodes: 41 Optional child node of NAND chip nodes:
42 Partitions: see mtd.yaml 42 Partitions: see mtd.yaml
43 43
44 Example: 44 Example:
45 nand-controller@70008000 { 45 nand-controller@70008000 {
46 compatible = "nvidia,tegra20-n 46 compatible = "nvidia,tegra20-nand";
47 reg = <0x70008000 0x100>; 47 reg = <0x70008000 0x100>;
48 interrupts = <GIC_SPI 24 IRQ_T 48 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&tegra_car TEGRA20_C 49 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
50 clock-names = "nand"; 50 clock-names = "nand";
51 resets = <&tegra_car 13>; 51 resets = <&tegra_car 13>;
52 reset-names = "nand"; 52 reset-names = "nand";
53 53
54 nand@0 { 54 nand@0 {
55 reg = <0>; 55 reg = <0>;
56 #address-cells = <1>; 56 #address-cells = <1>;
57 #size-cells = <1>; 57 #size-cells = <1>;
58 nand-bus-width = <8>; 58 nand-bus-width = <8>;
59 nand-on-flash-bbt; 59 nand-on-flash-bbt;
60 nand-ecc-algo = "bch"; 60 nand-ecc-algo = "bch";
61 nand-ecc-strength = <8 61 nand-ecc-strength = <8>;
62 wp-gpios = <&gpio TEGR 62 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
63 }; 63 };
64 }; 64 };
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