1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux 4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Generic register bitfield-based multipl !! 7 title: Generic register bitfield-based multiplexer controller bindings
8 8
9 maintainers: 9 maintainers:
10 - Peter Rosin <peda@axentia.se> 10 - Peter Rosin <peda@axentia.se>
11 11
12 description: |+ 12 description: |+
13 Define register bitfields to be used to cont 13 Define register bitfields to be used to control multiplexers. The parent
14 device tree node must be a device node to pr 14 device tree node must be a device node to provide register r/w access.
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - reg-mux # parent device of mux contr 19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux contr 20 - mmio-mux # parent device of mux controller is syscon device
21 21
22 reg: true 22 reg: true
23 23
24 '#mux-control-cells': 24 '#mux-control-cells':
25 const: 1 25 const: 1
26 26
27 mux-reg-masks: 27 mux-reg-masks:
28 $ref: /schemas/types.yaml#/definitions/uin !! 28 description: an array of register offset and pre-shifted bitfield mask
29 items: !! 29 pairs, each describing a single mux control.
30 items: <<
31 - description: register offset <<
32 - description: pre-shifted bitfield ma <<
33 description: Each entry pair describes a s <<
34 30
35 idle-states: true 31 idle-states: true
36 32
37 required: 33 required:
38 - compatible 34 - compatible
39 - mux-reg-masks 35 - mux-reg-masks
40 - '#mux-control-cells' 36 - '#mux-control-cells'
41 37
42 additionalProperties: false 38 additionalProperties: false
43 39
44 examples: 40 examples:
45 - | 41 - |
46 /* The parent device of mux controller is 42 /* The parent device of mux controller is not a syscon device. */
47 43
48 #include <dt-bindings/mux/mux.h> 44 #include <dt-bindings/mux/mux.h>
49 45
50 mux-controller { 46 mux-controller {
51 compatible = "reg-mux"; 47 compatible = "reg-mux";
52 #mux-control-cells = <1>; 48 #mux-control-cells = <1>;
53 mux-reg-masks = 49 mux-reg-masks =
54 <0x54 0xf8>, /* 0: reg 0x54, bits 50 <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
55 <0x54 0x07>; /* 1: reg 0x54, bits 51 <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
56 }; 52 };
57 53
58 mdio-mux-1 { 54 mdio-mux-1 {
59 compatible = "mdio-mux-multiplexer"; 55 compatible = "mdio-mux-multiplexer";
60 mux-controls = <&mux1 0>; 56 mux-controls = <&mux1 0>;
61 mdio-parent-bus = <&emdio1>; 57 mdio-parent-bus = <&emdio1>;
62 #address-cells = <1>; 58 #address-cells = <1>;
63 #size-cells = <0>; 59 #size-cells = <0>;
64 60
65 mdio@0 { 61 mdio@0 {
66 reg = <0x0>; 62 reg = <0x0>;
67 #address-cells = <1>; 63 #address-cells = <1>;
68 #size-cells = <0>; 64 #size-cells = <0>;
69 }; 65 };
70 66
71 mdio@8 { 67 mdio@8 {
72 reg = <0x8>; 68 reg = <0x8>;
73 #address-cells = <1>; 69 #address-cells = <1>;
74 #size-cells = <0>; 70 #size-cells = <0>;
75 }; 71 };
76 }; 72 };
77 73
78 mdio-mux-2 { 74 mdio-mux-2 {
79 compatible = "mdio-mux-multiplexer"; 75 compatible = "mdio-mux-multiplexer";
80 mux-controls = <&mux1 1>; 76 mux-controls = <&mux1 1>;
81 mdio-parent-bus = <&emdio2>; 77 mdio-parent-bus = <&emdio2>;
82 #address-cells = <1>; 78 #address-cells = <1>;
83 #size-cells = <0>; 79 #size-cells = <0>;
84 80
85 mdio@0 { 81 mdio@0 {
86 reg = <0x0>; 82 reg = <0x0>;
87 #address-cells = <1>; 83 #address-cells = <1>;
88 #size-cells = <0>; 84 #size-cells = <0>;
89 }; 85 };
90 86
91 mdio@1 { 87 mdio@1 {
92 reg = <0x1>; 88 reg = <0x1>;
93 #address-cells = <1>; 89 #address-cells = <1>;
94 #size-cells = <0>; 90 #size-cells = <0>;
95 }; 91 };
96 }; 92 };
97 93
98 - | 94 - |
99 /* The parent device of mux controller is 95 /* The parent device of mux controller is syscon device. */
100 96
101 #include <dt-bindings/mux/mux.h> 97 #include <dt-bindings/mux/mux.h>
102 syscon@1000 { 98 syscon@1000 {
>> 99 compatible = "fsl,imx7d-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
103 reg = <0x1000 0x100>; 100 reg = <0x1000 0x100>;
104 101
105 mux2: mux-controller { 102 mux2: mux-controller {
106 compatible = "mmio-mux"; 103 compatible = "mmio-mux";
107 #mux-control-cells = <1>; 104 #mux-control-cells = <1>;
108 105
109 mux-reg-masks = 106 mux-reg-masks =
110 <0x3 0x30>, /* 0: reg 0x3, bit 107 <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
111 <0x3 0x40>; /* 1: reg 0x3, bit 108 <0x3 0x40>; /* 1: reg 0x3, bit 6 */
112 idle-states = <MUX_IDLE_AS_IS>, <0 109 idle-states = <MUX_IDLE_AS_IS>, <0>;
113 }; 110 };
114 }; 111 };
115 112
116 video-mux { 113 video-mux {
117 compatible = "video-mux"; 114 compatible = "video-mux";
118 mux-controls = <&mux2 0>; 115 mux-controls = <&mux2 0>;
119 #address-cells = <1>; 116 #address-cells = <1>;
120 #size-cells = <0>; 117 #size-cells = <0>;
121 118
122 ports { 119 ports {
123 #address-cells = <1>; 120 #address-cells = <1>;
124 #size-cells = <0>; 121 #size-cells = <0>;
125 122
126 /* inputs 0..3 */ 123 /* inputs 0..3 */
127 port@0 { 124 port@0 {
128 reg = <0>; 125 reg = <0>;
129 }; 126 };
130 port@1 { 127 port@1 {
131 reg = <1>; 128 reg = <1>;
132 }; 129 };
133 port@2 { 130 port@2 {
134 reg = <2>; 131 reg = <2>;
135 }; 132 };
136 port@3 { 133 port@3 {
137 reg = <3>; 134 reg = <3>;
138 }; 135 };
139 136
140 /* output */ 137 /* output */
141 port@4 { 138 port@4 {
142 reg = <4>; 139 reg = <4>;
143 }; 140 };
144 }; 141 };
145 }; 142 };
146 ... 143 ...
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