1 # SPDX-License-Identifier: GPL-2.0+
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/adi,adi
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Analog Devices ADIN1200/ADIN1300 PHY
8
9 maintainers:
10 - Alexandru Tachici <alexandru.tachici@analog
11
12 description: |
13 Bindings for Analog Devices Industrial Ether
14
15 allOf:
16 - $ref: ethernet-phy.yaml#
17
18 properties:
19 adi,rx-internal-delay-ps:
20 description: |
21 RGMII RX Clock Delay used only when PHY
22 internal delay (phy-mode is 'rgmii-id' o
23 enum: [ 1600, 1800, 2000, 2200, 2400 ]
24 default: 2000
25
26 adi,tx-internal-delay-ps:
27 description: |
28 RGMII TX Clock Delay used only when PHY
29 internal delay (phy-mode is 'rgmii-id' o
30 enum: [ 1600, 1800, 2000, 2200, 2400 ]
31 default: 2000
32
33 adi,fifo-depth-bits:
34 description: |
35 When operating in RMII mode, this option
36 enum: [ 4, 8, 12, 16, 20, 24 ]
37 default: 8
38
39 adi,phy-output-clock:
40 description: |
41 Select clock output on GP_CLK pin. Two c
42 A 25MHz reference and a free-running 125
43 The phy can alternatively automatically
44 the 125MHz clocks based on its internal
45 $ref: /schemas/types.yaml#/definitions/str
46 enum:
47 - 25mhz-reference
48 - 125mhz-free-running
49 - adaptive-free-running
50
51 adi,phy-output-reference-clock:
52 description: Enable 25MHz reference clock
53 type: boolean
54
55 unevaluatedProperties: false
56
57 examples:
58 - |
59 ethernet {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 phy-mode = "rgmii-id";
64
65 ethernet-phy@0 {
66 reg = <0>;
67
68 adi,rx-internal-delay-ps = <1800>;
69 adi,tx-internal-delay-ps = <2200>;
70 };
71 };
72 - |
73 ethernet {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 phy-mode = "rmii";
78
79 ethernet-phy@1 {
80 reg = <1>;
81
82 adi,fifo-depth-bits = <16>;
83 };
84 };
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