1 CAN Device Tree Bindings 1 CAN Device Tree Bindings
2 ------------------------ 2 ------------------------
3 3
4 (c) 2006-2009 Secret Lab Technologies Ltd 4 (c) 2006-2009 Secret Lab Technologies Ltd
5 Grant Likely <grant.likely@secretlab.ca> 5 Grant Likely <grant.likely@secretlab.ca>
6 6
7 fsl,mpc5200-mscan nodes 7 fsl,mpc5200-mscan nodes
8 ----------------------- 8 -----------------------
9 In addition to the required compatible-, reg- 9 In addition to the required compatible-, reg- and interrupt-properties, you can
10 also specify which clock source shall be used 10 also specify which clock source shall be used for the controller:
11 11
12 - fsl,mscan-clock-source : a string describing 12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bu 13 are: "ip" for ip bus clock
14 "ref" for ref 14 "ref" for reference clock (XTAL)
15 "ref" is default in 15 "ref" is default in case this property is not
16 present. 16 present.
17 17
18 fsl,mpc5121-mscan nodes 18 fsl,mpc5121-mscan nodes
19 ----------------------- 19 -----------------------
20 In addition to the required compatible-, reg- 20 In addition to the required compatible-, reg- and interrupt-properties, you can
21 also specify which clock source and divider sh 21 also specify which clock source and divider shall be used for the controller:
22 22
23 - fsl,mscan-clock-source : a string describing 23 - fsl,mscan-clock-source : a string describing the clock source. Valid values
24 are: "ip" for ip bu 24 are: "ip" for ip bus clock
25 "ref" for refe 25 "ref" for reference clock
26 "sys" for syst 26 "sys" for system clock
27 If this property is 27 If this property is not present, an optimal CAN
28 clock source and fr 28 clock source and frequency based on the system
29 clock will be selec 29 clock will be selected. If this is not possible,
30 the reference clock 30 the reference clock will be used.
31 31
32 - fsl,mscan-clock-divider: for the reference a 32 - fsl,mscan-clock-divider: for the reference and system clock, an additional
33 clock divider can b 33 clock divider can be specified. By default, a
34 value of 1 is used. 34 value of 1 is used.
35 35
36 Note that the MPC5121 Rev. 1 processor is not 36 Note that the MPC5121 Rev. 1 processor is not supported.
37 37
38 Examples: 38 Examples:
39 can@1300 { 39 can@1300 {
40 compatible = "fsl,mpc5121-msca 40 compatible = "fsl,mpc5121-mscan";
41 interrupts = <12 0x8>; 41 interrupts = <12 0x8>;
42 interrupt-parent = <&ipic>; 42 interrupt-parent = <&ipic>;
43 reg = <0x1300 0x80>; 43 reg = <0x1300 0x80>;
44 }; 44 };
45 45
46 can@1380 { 46 can@1380 {
47 compatible = "fsl,mpc5121-msca 47 compatible = "fsl,mpc5121-mscan";
48 interrupts = <13 0x8>; 48 interrupts = <13 0x8>;
49 interrupt-parent = <&ipic>; 49 interrupt-parent = <&ipic>;
50 reg = <0x1380 0x80>; 50 reg = <0x1380 0x80>;
51 fsl,mscan-clock-source = "ref" 51 fsl,mscan-clock-source = "ref";
52 fsl,mscan-clock-divider = <3>; 52 fsl,mscan-clock-divider = <3>;
53 }; 53 };
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