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Linux/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml

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Diff markup

Differences between /Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml (Architecture i386) and /Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml (Architecture mips)


  1 # SPDX-License-Identifier: (GPL-2.0-only OR BS      1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2                                           2 %YAML 1.2
  3 ---                                                 3 ---
  4 $id: http://devicetree.org/schemas/net/can/st,      4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
  5 $schema: http://devicetree.org/meta-schemas/co      5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6                                                     6 
  7 title: STMicroelectronics bxCAN controller          7 title: STMicroelectronics bxCAN controller
  8                                                     8 
  9 description: STMicroelectronics BxCAN controll      9 description: STMicroelectronics BxCAN controller for CAN bus
 10                                                    10 
 11 maintainers:                                       11 maintainers:
 12   - Dario Binacchi <dario.binacchi@amarulasolut     12   - Dario Binacchi <dario.binacchi@amarulasolutions.com>
 13                                                    13 
 14 allOf:                                             14 allOf:
 15   - $ref: can-controller.yaml#                     15   - $ref: can-controller.yaml#
 16                                                    16 
 17 properties:                                        17 properties:
 18   compatible:                                      18   compatible:
 19     enum:                                          19     enum:
 20       - st,stm32f4-bxcan                           20       - st,stm32f4-bxcan
 21                                                    21 
 22   st,can-primary:                                  22   st,can-primary:
 23     description:                                   23     description:
 24       Primary mode of the bxCAN peripheral is      24       Primary mode of the bxCAN peripheral is only relevant if the chip has
 25       two CAN peripherals in dual CAN configur     25       two CAN peripherals in dual CAN configuration. In that case they share
 26       some of the required logic.                  26       some of the required logic.
 27       Not to be used if the peripheral is in s     27       Not to be used if the peripheral is in single CAN configuration.
 28       To avoid misunderstandings, it should be     28       To avoid misunderstandings, it should be noted that ST documentation
 29       uses the terms master instead of primary     29       uses the terms master instead of primary.
 30     type: boolean                                  30     type: boolean
 31                                                    31 
 32   st,can-secondary:                                32   st,can-secondary:
 33     description:                                   33     description:
 34       Secondary mode of the bxCAN peripheral i     34       Secondary mode of the bxCAN peripheral is only relevant if the chip
 35       has two CAN peripherals in dual CAN conf     35       has two CAN peripherals in dual CAN configuration. In that case they
 36       share some of the required logic.            36       share some of the required logic.
 37       Not to be used if the peripheral is in s     37       Not to be used if the peripheral is in single CAN configuration.
 38       To avoid misunderstandings, it should be     38       To avoid misunderstandings, it should be noted that ST documentation
 39       uses the terms slave instead of secondar     39       uses the terms slave instead of secondary.
 40     type: boolean                                  40     type: boolean
 41                                                    41 
 42   reg:                                             42   reg:
 43     maxItems: 1                                    43     maxItems: 1
 44                                                    44 
 45   interrupts:                                      45   interrupts:
 46     items:                                         46     items:
 47       - description: transmit interrupt            47       - description: transmit interrupt
 48       - description: FIFO 0 receive interrupt      48       - description: FIFO 0 receive interrupt
 49       - description: FIFO 1 receive interrupt      49       - description: FIFO 1 receive interrupt
 50       - description: status change error inter     50       - description: status change error interrupt
 51                                                    51 
 52   interrupt-names:                                 52   interrupt-names:
 53     items:                                         53     items:
 54       - const: tx                                  54       - const: tx
 55       - const: rx0                                 55       - const: rx0
 56       - const: rx1                                 56       - const: rx1
 57       - const: sce                                 57       - const: sce
 58                                                    58 
 59   resets:                                          59   resets:
 60     maxItems: 1                                    60     maxItems: 1
 61                                                    61 
 62   clocks:                                          62   clocks:
 63     maxItems: 1                                    63     maxItems: 1
 64                                                    64 
 65   st,gcan:                                         65   st,gcan:
 66     $ref: /schemas/types.yaml#/definitions/pha     66     $ref: /schemas/types.yaml#/definitions/phandle-array
 67     description:                                   67     description:
 68       The phandle to the gcan node which allow     68       The phandle to the gcan node which allows to access the 512-bytes
 69       SRAM memory shared by the two bxCAN cell     69       SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
 70       secondary) in dual CAN peripheral config     70       secondary) in dual CAN peripheral configuration.
 71                                                    71 
 72 required:                                          72 required:
 73   - compatible                                     73   - compatible
 74   - reg                                            74   - reg
 75   - interrupts                                     75   - interrupts
 76   - resets                                         76   - resets
 77   - clocks                                         77   - clocks
 78   - st,gcan                                        78   - st,gcan
 79                                                    79 
 80 additionalProperties: false                        80 additionalProperties: false
 81                                                    81 
 82 examples:                                          82 examples:
 83   - |                                              83   - |
 84     #include <dt-bindings/clock/stm32fx-clock.     84     #include <dt-bindings/clock/stm32fx-clock.h>
 85     #include <dt-bindings/mfd/stm32f4-rcc.h>       85     #include <dt-bindings/mfd/stm32f4-rcc.h>
 86                                                    86 
 87     can1: can@40006400 {                           87     can1: can@40006400 {
 88         compatible = "st,stm32f4-bxcan";           88         compatible = "st,stm32f4-bxcan";
 89         reg = <0x40006400 0x200>;                  89         reg = <0x40006400 0x200>;
 90         interrupts = <19>, <20>, <21>, <22>;       90         interrupts = <19>, <20>, <21>, <22>;
 91         interrupt-names = "tx", "rx0", "rx1",      91         interrupt-names = "tx", "rx0", "rx1", "sce";
 92         resets = <&rcc STM32F4_APB1_RESET(CAN1     92         resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
 93         clocks = <&rcc 0 STM32F4_APB1_CLOCK(CA     93         clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
 94         st,can-primary;                            94         st,can-primary;
 95         st,gcan = <&gcan>;                         95         st,gcan = <&gcan>;
 96     };                                             96     };
                                                      

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