1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/ingenic 4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: MAC in Ingenic SoCs !! 7 title: Bindings for MAC in Ingenic SoCs
8 8
9 maintainers: 9 maintainers:
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeet 10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
11 11
12 description: 12 description:
13 The Ethernet Media Access Controller in Inge 13 The Ethernet Media Access Controller in Ingenic SoCs.
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 enum: 17 enum:
18 - ingenic,jz4775-mac 18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac 19 - ingenic,x1000-mac
20 - ingenic,x1600-mac 20 - ingenic,x1600-mac
21 - ingenic,x1830-mac 21 - ingenic,x1830-mac
22 - ingenic,x2000-mac 22 - ingenic,x2000-mac
23 23
24 reg: 24 reg:
25 maxItems: 1 25 maxItems: 1
26 26
27 interrupts: 27 interrupts:
28 maxItems: 1 28 maxItems: 1
29 29
30 interrupt-names: 30 interrupt-names:
31 const: macirq 31 const: macirq
32 32
33 clocks: 33 clocks:
34 maxItems: 1 34 maxItems: 1
35 35
36 clock-names: 36 clock-names:
37 const: stmmaceth 37 const: stmmaceth
38 38
39 mode-reg: 39 mode-reg:
40 $ref: /schemas/types.yaml#/definitions/pha 40 $ref: /schemas/types.yaml#/definitions/phandle
41 description: An extra syscon register that 41 description: An extra syscon register that control ethernet interface and timing delay
42 42
43 rx-clk-delay-ps: 43 rx-clk-delay-ps:
44 description: RGMII receive clock delay def 44 description: RGMII receive clock delay defined in pico seconds
45 45
46 tx-clk-delay-ps: 46 tx-clk-delay-ps:
47 description: RGMII transmit clock delay de 47 description: RGMII transmit clock delay defined in pico seconds
48 48
49 required: 49 required:
50 - compatible 50 - compatible
51 - reg 51 - reg
52 - interrupts 52 - interrupts
53 - interrupt-names 53 - interrupt-names
54 - clocks 54 - clocks
55 - clock-names 55 - clock-names
56 - mode-reg 56 - mode-reg
57 57
58 additionalProperties: false 58 additionalProperties: false
59 59
60 examples: 60 examples:
61 - | 61 - |
62 #include <dt-bindings/clock/ingenic,x1000- 62 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
63 63
64 mac: ethernet@134b0000 { 64 mac: ethernet@134b0000 {
65 compatible = "ingenic,x1000-mac"; 65 compatible = "ingenic,x1000-mac";
66 reg = <0x134b0000 0x2000>; 66 reg = <0x134b0000 0x2000>;
67 67
68 interrupt-parent = <&intc>; 68 interrupt-parent = <&intc>;
69 interrupts = <55>; 69 interrupts = <55>;
70 interrupt-names = "macirq"; 70 interrupt-names = "macirq";
71 71
72 clocks = <&cgu X1000_CLK_MAC>; 72 clocks = <&cgu X1000_CLK_MAC>;
73 clock-names = "stmmaceth"; 73 clock-names = "stmmaceth";
74 74
75 mode-reg = <&mac_phy_ctrl>; 75 mode-reg = <&mac_phy_ctrl>;
76 }; 76 };
77 ... 77 ...
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