1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2018 Linaro Ltd. 2 # Copyright 2018 Linaro Ltd.
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/net/intel,i 5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: Intel IXP4xx ethernet 8 title: Intel IXP4xx ethernet
9 9
10 allOf: 10 allOf:
11 - $ref: ethernet-controller.yaml# 11 - $ref: ethernet-controller.yaml#
12 12
13 maintainers: 13 maintainers:
14 - Linus Walleij <linus.walleij@linaro.org> 14 - Linus Walleij <linus.walleij@linaro.org>
15 15
16 description: | 16 description: |
17 The Intel IXP4xx ethernet makes use of the I 17 The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network
18 Processing Engine) and the IXP4xx Queue Mana 18 Processing Engine) and the IXP4xx Queue Manager to process
19 the ethernet frames. It can optionally conta 19 the ethernet frames. It can optionally contain an MDIO bus to
20 talk to PHYs. 20 talk to PHYs.
21 21
22 properties: 22 properties:
23 compatible: 23 compatible:
24 const: intel,ixp4xx-ethernet 24 const: intel,ixp4xx-ethernet
25 25
26 reg: 26 reg:
27 maxItems: 1 27 maxItems: 1
28 description: Ethernet MMIO address range 28 description: Ethernet MMIO address range
29 29
30 queue-rx: 30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/pha 31 $ref: /schemas/types.yaml#/definitions/phandle-array
32 items: 32 items:
33 - items: 33 - items:
34 - description: phandle to the RX que 34 - description: phandle to the RX queue node
35 - description: RX queue instance to 35 - description: RX queue instance to use
36 description: phandle to the RX queue on th 36 description: phandle to the RX queue on the NPE
37 37
38 queue-txready: 38 queue-txready:
39 $ref: /schemas/types.yaml#/definitions/pha 39 $ref: /schemas/types.yaml#/definitions/phandle-array
40 items: 40 items:
41 - items: 41 - items:
42 - description: phandle to the TX REA 42 - description: phandle to the TX READY queue node
43 - description: TX READY queue instan 43 - description: TX READY queue instance to use
44 description: phandle to the TX READY queue 44 description: phandle to the TX READY queue on the NPE
45 45
46 phy-mode: true 46 phy-mode: true
47 47
48 phy-handle: true 48 phy-handle: true
49 49
50 intel,npe-handle: 50 intel,npe-handle:
51 $ref: /schemas/types.yaml#/definitions/pha 51 $ref: /schemas/types.yaml#/definitions/phandle-array
52 items: 52 items:
53 - items: 53 - items:
54 - description: phandle to the NPE th 54 - description: phandle to the NPE this ethernet instance is using
55 - description: the NPE instance to u 55 - description: the NPE instance to use
56 description: phandle to the NPE this ether 56 description: phandle to the NPE this ethernet instance is using
57 and the instance to use in the second ce 57 and the instance to use in the second cell
58 58
59 mdio: 59 mdio:
60 $ref: mdio.yaml# 60 $ref: mdio.yaml#
61 unevaluatedProperties: false 61 unevaluatedProperties: false
62 description: optional node for embedded MD 62 description: optional node for embedded MDIO controller
63 63
64 required: 64 required:
65 - compatible 65 - compatible
66 - reg 66 - reg
67 - queue-rx 67 - queue-rx
68 - queue-txready 68 - queue-txready
69 - intel,npe-handle 69 - intel,npe-handle
70 70
71 additionalProperties: false 71 additionalProperties: false
72 72
73 examples: 73 examples:
74 - | 74 - |
75 npe: npe@c8006000 { 75 npe: npe@c8006000 {
76 compatible = "intel,ixp4xx-network-proce 76 compatible = "intel,ixp4xx-network-processing-engine";
77 reg = <0xc8006000 0x1000>, <0xc8007000 0 77 reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
78 }; 78 };
79 79
80 ethernet@c8009000 { 80 ethernet@c8009000 {
81 compatible = "intel,ixp4xx-ethernet"; 81 compatible = "intel,ixp4xx-ethernet";
82 reg = <0xc8009000 0x1000>; 82 reg = <0xc8009000 0x1000>;
83 queue-rx = <&qmgr 4>; 83 queue-rx = <&qmgr 4>;
84 queue-txready = <&qmgr 21>; 84 queue-txready = <&qmgr 21>;
85 intel,npe-handle = <&npe 1>; 85 intel,npe-handle = <&npe 1>;
86 phy-mode = "rgmii"; 86 phy-mode = "rgmii";
87 phy-handle = <&phy1>; 87 phy-handle = <&phy1>;
88 }; 88 };
89 89
90 ethernet@c800c000 { 90 ethernet@c800c000 {
91 compatible = "intel,ixp4xx-ethernet"; 91 compatible = "intel,ixp4xx-ethernet";
92 reg = <0xc800c000 0x1000>; 92 reg = <0xc800c000 0x1000>;
93 queue-rx = <&qmgr 3>; 93 queue-rx = <&qmgr 3>;
94 queue-txready = <&qmgr 20>; 94 queue-txready = <&qmgr 20>;
95 intel,npe-handle = <&npe 2>; 95 intel,npe-handle = <&npe 2>;
96 phy-mode = "rgmii"; 96 phy-mode = "rgmii";
97 phy-handle = <&phy2>; 97 phy-handle = <&phy2>;
98 98
99 mdio { 99 mdio {
100 #address-cells = <1>; 100 #address-cells = <1>;
101 #size-cells = <0>; 101 #size-cells = <0>;
102 phy1: ethernet-phy@1 { 102 phy1: ethernet-phy@1 {
103 reg = <1>; 103 reg = <1>;
104 }; 104 };
105 phy2: ethernet-phy@2 { 105 phy2: ethernet-phy@2 {
106 reg = <2>; 106 reg = <2>;
107 }; 107 };
108 }; 108 };
109 }; 109 };
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