1 * Marvell PXA168 Ethernet Controller 1 * Marvell PXA168 Ethernet Controller
2 2
3 Required properties: 3 Required properties:
4 - compatible: should be "marvell,pxa168-eth". 4 - compatible: should be "marvell,pxa168-eth".
5 - reg: address and length of the register set 5 - reg: address and length of the register set for the device.
6 - interrupts: interrupt for the device. 6 - interrupts: interrupt for the device.
7 - clocks: pointer to the clock for the device. 7 - clocks: pointer to the clock for the device.
8 8
9 Optional properties: 9 Optional properties:
10 - port-id: Ethernet port number. Should be '0' 10 - port-id: Ethernet port number. Should be '0','1' or '2'.
11 - #address-cells: must be 1 when using sub-nod 11 - #address-cells: must be 1 when using sub-nodes.
12 - #size-cells: must be 0 when using sub-nodes. 12 - #size-cells: must be 0 when using sub-nodes.
13 - phy-handle: see ethernet.txt file in the sam 13 - phy-handle: see ethernet.txt file in the same directory.
14 !! 14 - local-mac-address: see ethernet.txt file in the same directory.
15 The MAC address will be determined using the o <<
16 defined in ethernet.txt. <<
17 15
18 Sub-nodes: 16 Sub-nodes:
19 Each PHY can be represented as a sub-node. Thi 17 Each PHY can be represented as a sub-node. This is not mandatory.
20 18
21 Sub-nodes required properties: 19 Sub-nodes required properties:
22 - reg: the MDIO address of the PHY. 20 - reg: the MDIO address of the PHY.
23 21
24 Example: 22 Example:
25 23
26 eth0: ethernet@f7b90000 { 24 eth0: ethernet@f7b90000 {
27 compatible = "marvell,pxa168-e 25 compatible = "marvell,pxa168-eth";
28 reg = <0xf7b90000 0x10000>; 26 reg = <0xf7b90000 0x10000>;
29 clocks = <&chip CLKID_GETH0>; 27 clocks = <&chip CLKID_GETH0>;
30 interrupts = <GIC_SPI 24 IRQ_T 28 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
31 #address-cells = <1>; 29 #address-cells = <1>;
32 #size-cells = <0>; 30 #size-cells = <0>;
33 phy-handle = <ðphy0>; 31 phy-handle = <ðphy0>;
34 32
35 ethphy0: ethernet-phy@0 { 33 ethphy0: ethernet-phy@0 {
36 reg = <0>; 34 reg = <0>;
37 }; 35 };
38 }; 36 };
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