1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/net/microch 4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Microchip Sparx5 Ethernet switch contro 7 title: Microchip Sparx5 Ethernet switch controller
8 8
9 maintainers: 9 maintainers:
10 - Steen Hegelund <steen.hegelund@microchip.co 10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com> 11 - Lars Povlsen <lars.povlsen@microchip.com>
12 12
13 description: | 13 description: |
14 The SparX-5 Enterprise Ethernet switch famil 14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanc 15 Enterprise switching features such as advanced TCAM-based VLAN and
16 QoS processing enabling delivery of differen 16 QoS processing enabling delivery of differentiated services, and
17 security through TCAM-based frame processing 17 security through TCAM-based frame processing using versatile content
18 aware processor (VCAP). 18 aware processor (VCAP).
19 19
20 IPv4/IPv6 Layer 3 (L3) unicast and multicast 20 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
21 with up to 18K IPv4/9K IPv6 unicast LPM entr 21 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
22 IPv6 (S,G) multicast groups. 22 IPv6 (S,G) multicast groups.
23 23
24 L3 security features include source guard an 24 L3 security features include source guard and reverse path
25 forwarding (uRPF) tasks. Additional L3 featu 25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
26 IP tunnels (IP over GRE/IP). 26 IP tunnels (IP over GRE/IP).
27 27
28 The SparX-5 switch family targets managed La 28 The SparX-5 switch family targets managed Layer 2 and Layer 3
29 equipment in SMB, SME, and Enterprise where 29 equipment in SMB, SME, and Enterprise where high port count
30 1G/2.5G/5G/10G switching with 10G/25G aggreg 30 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
31 31
32 properties: 32 properties:
33 $nodename: 33 $nodename:
34 pattern: "^switch@[0-9a-f]+$" 34 pattern: "^switch@[0-9a-f]+$"
35 35
36 compatible: 36 compatible:
37 const: microchip,sparx5-switch 37 const: microchip,sparx5-switch
38 38
39 reg: 39 reg:
40 items: 40 items:
41 - description: cpu target 41 - description: cpu target
42 - description: devices target 42 - description: devices target
43 - description: general control block tar 43 - description: general control block target
44 44
45 reg-names: 45 reg-names:
46 items: 46 items:
47 - const: cpu 47 - const: cpu
48 - const: devices 48 - const: devices
49 - const: gcb 49 - const: gcb
50 50
51 interrupts: 51 interrupts:
52 minItems: 1 52 minItems: 1
53 items: 53 items:
54 - description: register based extraction 54 - description: register based extraction
55 - description: frame dma based extractio 55 - description: frame dma based extraction
56 - description: ptp interrupt 56 - description: ptp interrupt
57 57
58 interrupt-names: 58 interrupt-names:
59 minItems: 1 59 minItems: 1
60 items: 60 items:
61 - const: xtr 61 - const: xtr
62 - const: fdma 62 - const: fdma
63 - const: ptp 63 - const: ptp
64 64
65 resets: 65 resets:
66 items: 66 items:
67 - description: Reset controller used for 67 - description: Reset controller used for switch core reset (soft reset)
68 68
69 reset-names: 69 reset-names:
70 items: 70 items:
71 - const: switch 71 - const: switch
72 72
73 mac-address: true 73 mac-address: true
74 74
75 ethernet-ports: 75 ethernet-ports:
76 type: object 76 type: object
77 additionalProperties: false <<
78 <<
79 properties: <<
80 '#address-cells': <<
81 const: 1 <<
82 '#size-cells': <<
83 const: 0 <<
84 <<
85 patternProperties: 77 patternProperties:
86 "^port@[0-9a-f]+$": 78 "^port@[0-9a-f]+$":
87 $ref: /schemas/net/ethernet-controller !! 79 type: object
88 unevaluatedProperties: false <<
89 80
90 properties: 81 properties:
>> 82 '#address-cells':
>> 83 const: 1
>> 84 '#size-cells':
>> 85 const: 0
>> 86
91 reg: 87 reg:
92 description: Switch port number 88 description: Switch port number
93 89
94 phys: 90 phys:
95 maxItems: 1 91 maxItems: 1
96 description: 92 description:
97 phandle of a Ethernet SerDes PHY 93 phandle of a Ethernet SerDes PHY. This defines which SerDes
98 instance will handle the Etherne 94 instance will handle the Ethernet traffic.
99 95
>> 96 phy-mode:
>> 97 description:
>> 98 This specifies the interface used by the Ethernet SerDes towards
>> 99 the PHY or SFP.
>> 100
100 microchip,bandwidth: 101 microchip,bandwidth:
101 description: Specifies bandwidth i 102 description: Specifies bandwidth in Mbit/s allocated to the port.
102 $ref: /schemas/types.yaml#/definit !! 103 $ref: "/schemas/types.yaml#/definitions/uint32"
103 maximum: 25000 104 maximum: 25000
104 105
>> 106 phy-handle:
>> 107 description:
>> 108 phandle of a Ethernet PHY. This is optional and if provided it
>> 109 points to the cuPHY used by the Ethernet SerDes.
>> 110
>> 111 sfp:
>> 112 description:
>> 113 phandle of an SFP. This is optional and used when not specifying
>> 114 a cuPHY. It points to the SFP node that describes the SFP used by
>> 115 the Ethernet SerDes.
>> 116
>> 117 managed: true
>> 118
105 microchip,sd-sgpio: 119 microchip,sd-sgpio:
106 description: 120 description:
107 Index of the ports Signal Detect 121 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
108 This is optional, and only neede 122 This is optional, and only needed if the default used index is
109 is not correct. 123 is not correct.
110 $ref: /schemas/types.yaml#/definit !! 124 $ref: "/schemas/types.yaml#/definitions/uint32"
111 minimum: 0 125 minimum: 0
112 maximum: 383 126 maximum: 383
113 127
114 required: 128 required:
115 - reg 129 - reg
116 - phys 130 - phys
117 - phy-mode 131 - phy-mode
118 - microchip,bandwidth 132 - microchip,bandwidth
119 133
120 oneOf: 134 oneOf:
121 - required: 135 - required:
122 - phy-handle 136 - phy-handle
123 - required: 137 - required:
124 - sfp 138 - sfp
125 - managed 139 - managed
126 140
127 required: 141 required:
128 - compatible 142 - compatible
129 - reg 143 - reg
130 - reg-names 144 - reg-names
131 - interrupts 145 - interrupts
132 - interrupt-names 146 - interrupt-names
>> 147 - resets
>> 148 - reset-names
133 - ethernet-ports 149 - ethernet-ports
134 150
135 additionalProperties: false 151 additionalProperties: false
136 152
137 examples: 153 examples:
138 - | 154 - |
139 #include <dt-bindings/interrupt-controller 155 #include <dt-bindings/interrupt-controller/arm-gic.h>
140 switch: switch@600000000 { 156 switch: switch@600000000 {
141 compatible = "microchip,sparx5-switch"; 157 compatible = "microchip,sparx5-switch";
142 reg = <0 0x401000>, 158 reg = <0 0x401000>,
143 <0x10004000 0x7fc000>, 159 <0x10004000 0x7fc000>,
144 <0x11010000 0xaf0000>; 160 <0x11010000 0xaf0000>;
145 reg-names = "cpu", "devices", "gcb"; 161 reg-names = "cpu", "devices", "gcb";
146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_ 162 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-names = "xtr"; 163 interrupt-names = "xtr";
148 resets = <&reset 0>; 164 resets = <&reset 0>;
149 reset-names = "switch"; 165 reset-names = "switch";
150 ethernet-ports { 166 ethernet-ports {
151 #address-cells = <1>; 167 #address-cells = <1>;
152 #size-cells = <0>; 168 #size-cells = <0>;
153 169
154 port0: port@0 { 170 port0: port@0 {
155 reg = <0>; 171 reg = <0>;
156 microchip,bandwidth = <1000>; 172 microchip,bandwidth = <1000>;
157 phys = <&serdes 13>; 173 phys = <&serdes 13>;
158 phy-handle = <&phy0>; 174 phy-handle = <&phy0>;
159 phy-mode = "qsgmii"; 175 phy-mode = "qsgmii";
160 }; 176 };
161 /* ... */ 177 /* ... */
162 /* Then the 25G interfaces */ 178 /* Then the 25G interfaces */
163 port60: port@60 { 179 port60: port@60 {
164 reg = <60>; 180 reg = <60>;
165 microchip,bandwidth = <25000>; 181 microchip,bandwidth = <25000>;
166 phys = <&serdes 29>; 182 phys = <&serdes 29>;
167 phy-mode = "10gbase-r"; 183 phy-mode = "10gbase-r";
168 sfp = <&sfp_eth60>; 184 sfp = <&sfp_eth60>;
169 managed = "in-band-status"; 185 managed = "in-band-status";
170 microchip,sd-sgpio = <365>; 186 microchip,sd-sgpio = <365>;
171 }; 187 };
172 port61: port@61 { 188 port61: port@61 {
173 reg = <61>; 189 reg = <61>;
174 microchip,bandwidth = <25000>; 190 microchip,bandwidth = <25000>;
175 phys = <&serdes 30>; 191 phys = <&serdes 30>;
176 phy-mode = "10gbase-r"; 192 phy-mode = "10gbase-r";
177 sfp = <&sfp_eth61>; 193 sfp = <&sfp_eth61>;
178 managed = "in-band-status"; 194 managed = "in-band-status";
179 microchip,sd-sgpio = <369>; 195 microchip,sd-sgpio = <369>;
180 }; 196 };
181 port62: port@62 { 197 port62: port@62 {
182 reg = <62>; 198 reg = <62>;
183 microchip,bandwidth = <25000>; 199 microchip,bandwidth = <25000>;
184 phys = <&serdes 31>; 200 phys = <&serdes 31>;
185 phy-mode = "10gbase-r"; 201 phy-mode = "10gbase-r";
186 sfp = <&sfp_eth62>; 202 sfp = <&sfp_eth62>;
187 managed = "in-band-status"; 203 managed = "in-band-status";
188 microchip,sd-sgpio = <373>; 204 microchip,sd-sgpio = <373>;
189 }; 205 };
190 port63: port@63 { 206 port63: port@63 {
191 reg = <63>; 207 reg = <63>;
192 microchip,bandwidth = <25000>; 208 microchip,bandwidth = <25000>;
193 phys = <&serdes 32>; 209 phys = <&serdes 32>;
194 phy-mode = "10gbase-r"; 210 phy-mode = "10gbase-r";
195 sfp = <&sfp_eth63>; 211 sfp = <&sfp_eth63>;
196 managed = "in-band-status"; 212 managed = "in-band-status";
197 microchip,sd-sgpio = <377>; 213 microchip,sd-sgpio = <377>;
198 }; 214 };
199 /* Finally the Management interface */ 215 /* Finally the Management interface */
200 port64: port@64 { 216 port64: port@64 {
201 reg = <64>; 217 reg = <64>;
202 microchip,bandwidth = <1000>; 218 microchip,bandwidth = <1000>;
203 phys = <&serdes 0>; 219 phys = <&serdes 0>;
204 phy-handle = <&phy64>; 220 phy-handle = <&phy64>;
205 phy-mode = "sgmii"; 221 phy-mode = "sgmii";
206 mac-address = [ 00 00 00 01 02 03 ]; 222 mac-address = [ 00 00 00 01 02 03 ];
207 }; 223 };
208 }; 224 };
209 }; 225 };
210 226
211 ... 227 ...
212 # vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft= 228 # vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :
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